[llvm] r262661 - [X86][AVX512BW] Fixed 512-bit PSHUFB shuffle mask decode and added combine test.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 3 13:55:01 PST 2016


Author: rksimon
Date: Thu Mar  3 15:55:01 2016
New Revision: 262661

URL: http://llvm.org/viewvc/llvm-project?rev=262661&view=rev
Log:
[X86][AVX512BW] Fixed 512-bit PSHUFB shuffle mask decode and added combine test.

PSHUFB decoder was assuming that input was 128 or 256-bit vector only.

Added:
    llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
Modified:
    llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp

Modified: llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp?rev=262661&r1=262660&r2=262661&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp (original)
+++ llvm/trunk/lib/Target/X86/Utils/X86ShuffleDecode.cpp Thu Mar  3 15:55:01 2016
@@ -314,9 +314,9 @@ void DecodePSHUFBMask(ArrayRef<uint64_t>
       ShuffleMask.push_back(M);
       continue;
     }
-    // For AVX vectors with 32 bytes the base of the shuffle is the half of
-    // the vector we're inside.
-    int Base = i < 16 ? 0 : 16;
+    // For 256/512-bit vectors the base of the shuffle is the 128-bit
+    // subvector we're inside.
+    int Base = (i / 16) * 16;
     // If the high bit (7) of the byte is set, the element is zeroed.
     if (M & (1 << 7))
       ShuffleMask.push_back(SM_SentinelZero);

Added: llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll?rev=262661&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll Thu Mar  3 15:55:01 2016
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512bw | FileCheck %s
+
+declare <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)
+
+define <64 x i8> @combine_pshufb_identity(<64 x i8> %x0) {
+; CHECK-LABEL: combine_pshufb_identity:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    retq
+  %select = bitcast <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1> to <64 x i8>
+  %mask = bitcast <16 x i32> <i32 202182159, i32 134810123, i32 67438087, i32 66051, i32 202182159, i32 134810123, i32 67438087, i32 66051, i32 202182159, i32 134810123, i32 67438087, i32 66051, i32 202182159, i32 134810123, i32 67438087, i32 66051> to <64 x i8>
+  %res0 = call <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8> %x0, <64 x i8> %mask, <64 x i8> %select, i64 -1)
+  %res1 = call <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8> %res0, <64 x i8> %mask, <64 x i8> %select, i64 -1)
+  ret <64 x i8> %res1
+}




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