[llvm] r262579 - AMDGPU: Insert two S_NOP instructions for every high level source statement.
David Blaikie via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 3 10:42:50 PST 2016
Test coverage?
On Wed, Mar 2, 2016 at 7:53 PM, Tom Stellard via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: tstellar
> Date: Wed Mar 2 21:53:29 2016
> New Revision: 262579
>
> URL: http://llvm.org/viewvc/llvm-project?rev=262579&view=rev
> Log:
> AMDGPU: Insert two S_NOP instructions for every high level source
> statement.
>
> Patch by: Konstantin Zhuravlyov
>
> Summary: Tools, such as debugger, need to pause execution based on user
> input (i.e. breakpoint). In order to do this, two S_NOP instructions are
> inserted for each high level source statement: one before first isa
> instruction of high level source statement, and one after last isa
> instruction of high level source statement. Further, debugger may replace
> S_NOP instructions with S_TRAP instructions based on user input.
>
What behavior do you intend if there are multiple separate instances of the
same line:
A
B
A
C
As it stands you'll get a NOP before the first A and a NOP after the last A
(for A) but not at the end of the first A or the start of the second?
Also, it seems like you'll end up with two NOPs for every transition
(modulo the above oddity) - eg: A, B, C -> NOP, A, NOP, NOP, B, NOP, NOP, C
Is that intentional? To what end? & why's this scheme necessary compared to
debuggers on existing platforms that don't need all these NOPs to be able
to replace with traps, etc?
(& why the leading NOP, but not the trailing NOP?)
>
> Reviewers: tstellarAMD, arsenm
>
> Subscribers: echristo, dblaikie, arsenm, llvm-commits
>
> Differential Revision: http://reviews.llvm.org/D17454
>
> Added:
> llvm/trunk/lib/Target/AMDGPU/SIInsertNopsPass.cpp
> Modified:
> llvm/trunk/lib/Target/AMDGPU/AMDGPU.h
> llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
> llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.h?rev=262579&r1=262578&r2=262579&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPU.h (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.h Wed Mar 2 21:53:29 2016
> @@ -49,6 +49,7 @@ FunctionPass *createSIFixControlFlowLive
> FunctionPass *createSIFixSGPRCopiesPass();
> FunctionPass *createSIFixSGPRLiveRangesPass();
> FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
> +FunctionPass *createSIInsertNopsPass();
> FunctionPass *createSIInsertWaitsPass();
>
> ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C);
> @@ -97,6 +98,9 @@ extern char &AMDGPUAnnotateUniformValues
> void initializeSIAnnotateControlFlowPass(PassRegistry&);
> extern char &SIAnnotateControlFlowPassID;
>
> +void initializeSIInsertNopsPass(PassRegistry&);
> +extern char &SIInsertNopsID;
> +
> void initializeSIInsertWaitsPass(PassRegistry&);
> extern char &SIInsertWaitsID;
>
>
> Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=262579&r1=262578&r2=262579&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Wed Mar 2
> 21:53:29 2016
> @@ -30,6 +30,7 @@
> #include "llvm/IR/Verifier.h"
> #include "llvm/MC/MCAsmInfo.h"
> #include "llvm/IR/LegacyPassManager.h"
> +#include "llvm/Support/CommandLine.h"
> #include "llvm/Support/TargetRegistry.h"
> #include "llvm/Support/raw_os_ostream.h"
> #include "llvm/Transforms/IPO.h"
> @@ -54,6 +55,7 @@ extern "C" void LLVMInitializeAMDGPUTarg
> initializeAMDGPUAnnotateUniformValuesPass(*PR);
> initializeAMDGPUPromoteAllocaPass(*PR);
> initializeSIAnnotateControlFlowPass(*PR);
> + initializeSIInsertNopsPass(*PR);
> initializeSIInsertWaitsPass(*PR);
> initializeSILowerControlFlowPass(*PR);
> }
> @@ -145,6 +147,12 @@ GCNTargetMachine::GCNTargetMachine(const
>
> //===----------------------------------------------------------------------===//
>
> namespace {
> +
> +cl::opt<bool> InsertNops(
> + "amdgpu-insert-nops",
> + cl::desc("Insert two nop instructions for each high level source
> statement"),
> + cl::init(false));
> +
> class AMDGPUPassConfig : public TargetPassConfig {
> public:
> AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
> @@ -364,6 +372,9 @@ void GCNPassConfig::addPreSched2() {
> void GCNPassConfig::addPreEmitPass() {
> addPass(createSIInsertWaitsPass(), false);
> addPass(createSILowerControlFlowPass(), false);
> + if (InsertNops) {
> + addPass(createSIInsertNopsPass(), false);
> + }
>
We usually skip {} on single-line blocks ^ (though I don't think it's a
style guide rule).
> }
>
> TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM)
> {
>
> Modified: llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt?rev=262579&r1=262578&r2=262579&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/AMDGPU/CMakeLists.txt Wed Mar 2 21:53:29 2016
> @@ -51,6 +51,7 @@ add_llvm_target(AMDGPUCodeGen
> SIFixSGPRLiveRanges.cpp
> SIFoldOperands.cpp
> SIFrameLowering.cpp
> + SIInsertNopsPass.cpp
> SIInsertWaits.cpp
> SIInstrInfo.cpp
> SIISelLowering.cpp
>
> Added: llvm/trunk/lib/Target/AMDGPU/SIInsertNopsPass.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInsertNopsPass.cpp?rev=262579&view=auto
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIInsertNopsPass.cpp (added)
> +++ llvm/trunk/lib/Target/AMDGPU/SIInsertNopsPass.cpp Wed Mar 2 21:53:29
> 2016
> @@ -0,0 +1,94 @@
> +//===--- SIInsertNopsPass.cpp - Use predicates for control flow
> -----------===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
>
> +//===----------------------------------------------------------------------===//
> +//
> +/// \file
> +/// \brief Insert two S_NOP instructions for every high level source
> statement.
> +///
> +/// Tools, such as debugger, need to pause execution based on user input
> (i.e.
> +/// breakpoint). In order to do this, two S_NOP instructions are inserted
> for
> +/// each high level source statement: one before first isa instruction of
> high
> +/// level source statement, and one after last isa instruction of high
> level
> +/// source statement. Further, debugger may replace S_NOP instructions
> with
> +/// S_TRAP instructions based on user input.
> +//
>
> +//===----------------------------------------------------------------------===//
> +
> +#include "SIInstrInfo.h"
> +#include "llvm/ADT/DenseMap.h"
> +#include "llvm/CodeGen/MachineFunction.h"
> +#include "llvm/CodeGen/MachineFunctionPass.h"
> +#include "llvm/CodeGen/MachineInstrBuilder.h"
> +using namespace llvm;
> +
> +#define DEBUG_TYPE "si-insert-nops"
> +#define PASS_NAME "SI Insert Nops"
> +
> +namespace {
> +
> +class SIInsertNops : public MachineFunctionPass {
> +public:
> + static char ID;
> +
> + SIInsertNops() : MachineFunctionPass(ID) { }
> + const char *getPassName() const override { return PASS_NAME; }
> +
> + bool runOnMachineFunction(MachineFunction &MF) override;
> +};
> +
> +} // anonymous namespace
> +
> +INITIALIZE_PASS(SIInsertNops, DEBUG_TYPE, PASS_NAME, false, false)
> +
> +char SIInsertNops::ID = 0;
> +char &llvm::SIInsertNopsID = SIInsertNops::ID;
> +
> +FunctionPass *llvm::createSIInsertNopsPass() {
> + return new SIInsertNops();
> +}
> +
> +bool SIInsertNops::runOnMachineFunction(MachineFunction &MF) {
> + const SIInstrInfo *TII =
> + static_cast<const SIInstrInfo*>(MF.getSubtarget().getInstrInfo());
> +
> + DenseMap<unsigned, MachineBasicBlock::iterator> LineToInst;
> + for (auto MBB = MF.begin(); MBB != MF.end(); ++MBB) {
>
Range-for ^ ?
> + for (auto MI = MBB->begin(); MI != MBB->end(); ++MI) {
> + if (MI->isDebugValue() || !MI->getDebugLoc()) {
> + continue;
> + }
> + auto DL = MI->getDebugLoc();
> + auto CL = DL.getLine();
> + auto LineToInstEntry = LineToInst.find(CL);
> + if (LineToInstEntry == LineToInst.end()) {
> + BuildMI(*MBB, *MI, DL, TII->get(AMDGPU::S_NOP))
> + .addImm(0);
> + LineToInst.insert(std::make_pair(CL, MI));
+ } else {
> + LineToInstEntry->second = MI;
> + }
> + }
> + }
> + for (auto LineToInstEntry = LineToInst.begin();
> + LineToInstEntry != LineToInst.end(); ++LineToInstEntry) {
>
Range for ^
> + auto MBB = LineToInstEntry->second->getParent();
> + auto DL = LineToInstEntry->second->getDebugLoc();
> + MachineBasicBlock::iterator MI = LineToInstEntry->second;
> + ++MI;
> + if (MI != MBB->end()) {
> + BuildMI(*MBB, *MI, DL, TII->get(AMDGPU::S_NOP))
> + .addImm(0);
> + }
> + }
> + MachineBasicBlock &MBB = MF.front();
> + MachineInstr &MI = MBB.front();
> + BuildMI(MBB, MI, DebugLoc(), TII->get(AMDGPU::S_NOP))
> + .addImm(0);
> +
> + return true;
> +}
>
>
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