[llvm] r262594 - Revert "[ARM] Merging 64-bit divmod lib calls into one"

[Renato Golin via llvm-commits]

Author: rengolin
Date: Thu Mar  3 02:57:44 2016
New Revision: 262594

URL: http://llvm.org/viewvc/llvm-project?rev=262594&view=rev
Log:
Revert "[ARM] Merging 64-bit divmod lib calls into one"

This reverts commit r262507, which broke some ARM buildbots.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/divmod-eabi.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=262594&r1=262593&r2=262594&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar  3 02:57:44 2016
@@ -2153,9 +2153,8 @@ SDValue DAGCombiner::useDivRem(SDNode *N
   if (Node->use_empty())
     return SDValue(); // This is a dead node, leave it alone.
 
-  // DivMod lib calls can still work on non-legal types if using lib-calls.
   EVT VT = Node->getValueType(0);
-  if (VT.isVector() || !VT.isInteger())
+  if (!TLI.isTypeLegal(VT))
     return SDValue();
 
   unsigned Opcode = Node->getOpcode();

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=262594&r1=262593&r2=262594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Mar  3 02:57:44 2016
@@ -809,8 +809,6 @@ ARMTargetLowering::ARMTargetLowering(con
 
     setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
     setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
-    setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
-    setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
   } else {
     setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
     setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
@@ -7056,13 +7054,6 @@ void ARMTargetLowering::ReplaceNodeResul
   case ISD::UREM:
     Res = LowerREM(N, DAG);
     break;
-  case ISD::SDIVREM:
-  case ISD::UDIVREM:
-    Res = LowerDivRem(SDValue(N, 0), DAG);
-    assert(Res.getNumOperands() == 2 && "DivRem needs two values");
-    Results.push_back(Res.getValue(0));
-    Results.push_back(Res.getValue(1));
-    return;
   case ISD::READCYCLECOUNTER:
     ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
     return;

Modified: llvm/trunk/test/CodeGen/ARM/divmod-eabi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/divmod-eabi.ll?rev=262594&r1=262593&r2=262594&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/divmod-eabi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/divmod-eabi.ll Thu Mar  3 02:57:44 2016
@@ -79,6 +79,7 @@ entry:
   ret i32 %add2
 }
 
+; FIXME: AEABI is not lowering long u/srem into u/ldivmod
 define i64 @longf(i64 %a, i64 %b) {
 ; EABI-LABEL: longf:
 ; DARWIN-LABEL: longf:
@@ -86,9 +87,6 @@ entry:
   %div = sdiv i64 %a, %b
   %rem = srem i64 %a, %b
 ; EABI: __aeabi_ldivmod
-; EABI-NEXT: adds r0
-; EABI-NEXT: adc r1
-; EABI-NOT: __aeabi_ldivmod
 ; DARWIN: ___divdi3
 ; DARWIN: mov [[div1:r[0-9]+]], r0
 ; DARWIN: mov [[div2:r[0-9]+]], r1