[PATCH] D17843: MachineSink: make shouldSink a TII target hook

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For us, this is useful because we generally want to sink register sequences on our target (otherwise they can act as a barrier and stop us from sinking other stuff). But it should be generally straightforward and useful for any other target to override this and decide that there are things they do or don't want to sink.

Repository:
  rL LLVM

http://reviews.llvm.org/D17843

Files:
  include/llvm/Target/TargetInstrInfo.h
  lib/CodeGen/MachineSink.cpp

Index: lib/CodeGen/MachineSink.cpp
===================================================================
--- lib/CodeGen/MachineSink.cpp
+++ lib/CodeGen/MachineSink.cpp
@@ -469,10 +469,6 @@
   return true;
 }
 
-static bool AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) {
-  return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence();
-}
-
 /// collectDebgValues - Scan instructions following MI and collect any
 /// matching DBG_VALUEs.
 static void collectDebugValues(MachineInstr *MI,
@@ -679,7 +675,7 @@
                                      AllSuccsCache &AllSuccessors) {
   // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to
   // be close to the source to make it easier to coalesce.
-  if (AvoidsSinking(MI, MRI))
+  if (!TII->shouldSink(*MI))
     return false;
 
   // Check if it's safe to move the instruction.
Index: include/llvm/Target/TargetInstrInfo.h
===================================================================
--- include/llvm/Target/TargetInstrInfo.h
+++ include/llvm/Target/TargetInstrInfo.h
@@ -215,6 +215,15 @@
     return MI->isAsCheapAsAMove();
   }
 
+  /// Return true if the instruction should be sunk by MachineSink.
+  ///
+  /// MachineSink determines on its own whether the instruction is safe to sink;
+  /// this gives the target a hook to override the default behavior with regards
+  /// to which instructions should be sunk.
+  virtual bool shouldSink(const MachineInstr &MI) const {
+    return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence();
+  }
+
   /// Re-issue the specified 'original' instruction at the
   /// specific location targeting a new destination register.
   /// The register in Orig->getOperand(0).getReg() will be substituted by


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