[llvm] r262540 - [AArch64] add tests to demonstrate existing codegen for PR26819

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Wed Mar  2 17:22:03 2016
New Revision: 262540

URL: http://llvm.org/viewvc/llvm-project?rev=262540&view=rev
Log:
[AArch64] add tests to demonstrate existing codegen for PR26819

Modified:
    llvm/trunk/test/CodeGen/AArch64/neon-compare-instructions.ll

Modified: llvm/trunk/test/CodeGen/AArch64/neon-compare-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-compare-instructions.ll?rev=262540&r1=262539&r2=262540&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-compare-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-compare-instructions.ll Wed Mar  2 17:22:03 2016
@@ -801,6 +801,71 @@ define <2 x i64> @cmgez2xi64(<2 x i64> %
 	ret <2 x i64> %tmp4
 }
 
+; FIXME: The following 7 tests could be optimized to cmgez to save an instruction.
+
+define <8 x i8> @cmgez8xi8_alt(<8 x i8> %A) {
+; CHECK-LABEL: cmgez8xi8_alt:
+; CHECK:       sshr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #7
+; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+  %sign = ashr <8 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %not = xor <8 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  ret <8 x i8> %not
+}
+
+define <16 x i8> @cmgez16xi8_alt(<16 x i8> %A) {
+; CHECK-LABEL: cmgez16xi8_alt:
+; CHECK:       sshr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #7
+; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+  %sign = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  %not = xor <16 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  ret <16 x i8> %not
+}
+
+define <4 x i16> @cmgez4xi16_alt(<4 x i16> %A) {
+; CHECK-LABEL: cmgez4xi16_alt:
+; CHECK:       sshr {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #15
+; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+  %sign = ashr <4 x i16> %A, <i16 15, i16 15, i16 15, i16 15>
+  %not = xor <4 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1>
+  ret <4 x i16> %not
+}
+
+define <8 x i16> @cmgez8xi16_alt(<8 x i16> %A) {
+; CHECK-LABEL: cmgez8xi16_alt:
+; CHECK:       sshr {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #15
+; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+  %sign = ashr <8 x i16> %A, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %not = xor <8 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  ret <8 x i16> %not
+}
+
+define <2 x i32> @cmgez2xi32_alt(<2 x i32> %A) {
+; CHECK-LABEL: cmgez2xi32_alt:
+; CHECK:       sshr {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #31
+; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+  %sign = ashr <2 x i32> %A, <i32 31, i32 31>
+  %not = xor <2 x i32> %sign, <i32 -1, i32 -1>
+  ret <2 x i32> %not
+}
+
+define <4 x i32> @cmgez4xi32_alt(<4 x i32> %A) {
+; CHECK-LABEL: cmgez4xi32_alt:
+; CHECK:       sshr {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #31
+; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+  %sign = ashr <4 x i32> %A, <i32 31, i32 31, i32 31, i32 31>
+  %not = xor <4 x i32> %sign, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %not
+}
+
+define <2 x i64> @cmgez2xi64_alt(<2 x i64> %A) {
+; CHECK-LABEL: cmgez2xi64_alt:
+; CHECK:       sshr {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #63
+; CHECK-NEXT:  {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+  %sign = ashr <2 x i64> %A, <i64 63, i64 63>
+  %not = xor <2 x i64> %sign, <i64 -1, i64 -1>
+  ret <2 x i64> %not
+}
+
 
 define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
 ; CHECK-LABEL: cmgtz8xi8: