[PATCH] D17781: Codegen: [PPC] Word Rotates are Zero Extending

[Kyle Butt via llvm-commits]

iteratee removed rL LLVM as the repository for this revision.
iteratee updated this revision to Diff 49658.
iteratee added a comment.

Added an operand check to make sure that we only perform this optimization in the case where the mask causes the upper 32 bits to be zeroed out.

Also add a test case to verify that it fires in the correct case, and doesn't fire in the incorrect case.


http://reviews.llvm.org/D17781

Files:
  lib/Target/PowerPC/PPCInstrInfo.cpp
  test/CodeGen/PowerPC/rlwinm-zero-ext.ll

Index: test/CodeGen/PowerPC/rlwinm-zero-ext.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/rlwinm-zero-ext.ll
@@ -0,0 +1,34 @@
+; RUN: llc -O2 < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; CHECK-LABEL: test1
+define i8 @test1(i32 %a) {
+entry:
+; CHECK-NOT: rlwinm {{{[0-9]+}}}, {{[0-9]+}}, 0, 24, 27
+; CHECK: rlwinm. [[REG:[0-9]+]], {{[0-9]+}}, 0, 24, 27
+; CHECK-NOT: cmplwi [[REG]], 0
+; CHECK: beq 0
+  %0 = and i32 %a, 240
+  %1 = icmp eq i32 %0, 0
+  br i1 %1, label %eq0, label %neq0
+eq0:
+  ret i8 102
+neq0:
+  ret i8 116
+}
+
+; CHECK-LABEL: test2
+define i8 @test2(i32 %a) {
+entry:
+; CHECK: rlwinm [[REG:[0-9]+]], {{[0-9]+}}, 0, 28, 23
+; CHECK: cmplwi [[REG]], 0
+; CHECK: beq 0
+  %0 = and i32 %a, -241
+  %1 = icmp eq i32 %0, 0
+  br i1 %1, label %eq0, label %neq0
+eq0:
+  ret i8 102
+neq0:
+  ret i8 116
+}
Index: lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.cpp
+++ lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1554,6 +1554,11 @@
   if (!MI) return false;
   int MIOpC = MI->getOpcode();
 
+  // 32-bit rotate and mask instructions are zero extending only if MB <= ME
+  bool isZeroExtendingRotate  =
+      (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM)
+      && MI->getOperand(3).getImm() <= MI->getOperand(4).getImm();
+
   bool equalityOnly = false;
   bool noSub = false;
   if (isPPC64) {
@@ -1572,7 +1577,8 @@
       // zero-extending.
       if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
           MIOpC == PPC::SLW    || MIOpC == PPC::SLWo ||
-          MIOpC == PPC::SRW    || MIOpC == PPC::SRWo) {
+          MIOpC == PPC::SRW    || MIOpC == PPC::SRWo ||
+          isZeroExtendingRotate) {
         noSub = true;
         equalityOnly = true;
       } else


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