[PATCH] D17373: [mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for microMIPS is generated.
Milena Vujosevic Janicic via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 2 02:17:04 PST 2016
milena.vujosevic.janicic updated this revision to Diff 49590.
milena.vujosevic.janicic added a comment.
Simplified test case
http://reviews.llvm.org/D17373
Files:
lib/Target/Mips/MicroMips32r6InstrFormats.td
lib/Target/Mips/MicroMips32r6InstrInfo.td
test/CodeGen/Mips/micromips-or16.ll
Index: test/CodeGen/Mips/micromips-or16.ll
===================================================================
--- test/CodeGen/Mips/micromips-or16.ll
+++ test/CodeGen/Mips/micromips-or16.ll
@@ -1,8 +1,21 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
+; RUN: llc -O0 -march=mips -mcpu=mips32r2 -mattr=+micromips \
+; RUN: -asm-show-inst < %s | FileCheck %s
+
+define i32 @f(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: f
+; CHECK-NOT: OR16_MMR6
+ %1 = or i32 %a, %b
+ br label %b1
+b1:
+ ret i32 %1
+}
define i32 @main() {
entry:
+; CHECK-LABEL: main
+; CHECK: or16
%retval = alloca i32, align 4
%a = alloca i32, align 4
%b = alloca i32, align 4
@@ -14,5 +27,3 @@
store i32 %or, i32* %a, align 4
ret i32 0
}
-
-; CHECK: or16
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -830,7 +830,7 @@
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
- MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+ MMR6Arch<"sdbbp16">;
class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
dag OutOperandList = (outs GPR32Opnd:$rt);
Index: lib/Target/Mips/MicroMips32r6InstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrFormats.td
+++ lib/Target/Mips/MicroMips32r6InstrFormats.td
@@ -751,7 +751,7 @@
let Inst{3-0} = 0b0000;
}
-class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
+class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
bits<3> rt;
bits<3> rs;
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