[llvm] r262358 - DAGCombiner: Turn extract of bitcasted integer into truncate

[Evgenii Stepanov via llvm-commits]

Hi,

this change breaks this chromium bot:
https://build.chromium.org/p/chromium.fyi/builders/ClangToTLinux/builds/4492/steps/compile/logs/stdio

SelectionDAG.cpp:3121: llvm::SDValue
llvm::SelectionDAG::getNode(unsigned int, llvm::SDLoc, llvm::EVT,
llvm::SDValue): Assertion `VT.isInteger() &&
Operand.getValueType().isInteger() && "Invalid TRUNCATE!"' failed.

I'm minimizing the test case. Would you mind reverting in the meantime?

On Tue, Mar 1, 2016 at 10:01 AM, Matt Arsenault via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: arsenm
> Date: Tue Mar  1 12:01:37 2016
> New Revision: 262358
>
> URL: http://llvm.org/viewvc/llvm-project?rev=262358&view=rev
> Log:
> DAGCombiner: Turn extract of bitcasted integer into truncate
>
> This reduces the number of bitcast nodes and generally cleans up the
> DAG when bitcasting between integers and vectors everywhere.
>
> Added:
>     llvm/trunk/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=262358&r1=262357&r2=262358&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Mar  1 12:01:37 2016
> @@ -12180,6 +12180,14 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR
>      // converts.
>    }
>
> +  // extract_vector_elt (v2i32 (bitcast i64:x)), 0 -> i32 (trunc i64:x)
> +  if (ConstEltNo && InVec.getOpcode() == ISD::BITCAST && InVec.hasOneUse() &&
> +      ConstEltNo->isNullValue()) {
> +    SDValue BCSrc = InVec.getOperand(0);
> +    if (BCSrc.getValueType().isScalarInteger())
> +      return DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, BCSrc);
> +  }
> +
>    // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
>    // We only perform this optimization before the op legalization phase because
>    // we may introduce new vector instructions which are not backed by TD
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=262358&r1=262357&r2=262358&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Mar  1 12:01:37 2016
> @@ -24850,13 +24850,7 @@ static SDValue PerformEXTRACT_VECTOR_ELT
>    if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
>        N->getValueType(0) == MVT::i32 &&
>        InputVector.getValueType() == MVT::v2i32) {
> -
> -    // The bitcast source is a direct mmx result.
>      SDValue MMXSrc = InputVector.getNode()->getOperand(0);
> -    if (MMXSrc.getValueType() == MVT::x86mmx)
> -      return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
> -                         N->getValueType(0),
> -                         InputVector.getNode()->getOperand(0));
>
>      // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
>      if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
> @@ -27940,11 +27934,22 @@ static SDValue combineVectorTruncation(S
>
>  static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
>                                        const X86Subtarget &Subtarget) {
> +
> +  SDValue Src = N->getOperand(0);
> +
>    // Try to detect AVG pattern first.
> -  if (SDValue Avg = detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG,
> +  if (SDValue Avg = detectAVGPattern(Src, N->getValueType(0), DAG,
>                                       Subtarget, SDLoc(N)))
>      return Avg;
>
> +  // The bitcast source is a direct mmx result.
> +  // Detect bitcasts between i32 to x86mmx
> +  if (Src.getOpcode() == ISD::BITCAST && N->getValueType(0) == MVT::i32) {
> +    SDValue BCSrc = Src.getOperand(0);
> +    if (BCSrc.getValueType() == MVT::x86mmx)
> +      return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(N), MVT::i32, BCSrc);
> +  }
> +
>    return combineVectorTruncation(N, DAG, Subtarget);
>  }
>
>
> Added: llvm/trunk/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/extractelt-to-trunc.ll?rev=262358&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/extractelt-to-trunc.ll (added)
> +++ llvm/trunk/test/CodeGen/AMDGPU/extractelt-to-trunc.ll Tue Mar  1 12:01:37 2016
> @@ -0,0 +1,17 @@
> +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
> +
> +; Make sure the add and load are reduced to 32-bits even with the
> +; bitcast to vector.
> +; GCN-LABEL: {{^}}bitcast_int_to_vector_extract_0:
> +; GCN-DAG: s_load_dword [[B:s[0-9]+]]
> +; GCN-DAG: buffer_load_dword [[A:v[0-9]+]]
> +; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, [[B]], [[A]]
> +; GCN: buffer_store_dword [[ADD]]
> +define void @bitcast_int_to_vector_extract_0(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) {
> +   %a = load i64, i64 addrspace(1)* %in
> +   %add = add i64 %a, %b
> +   %val.bc = bitcast i64 %add to <2 x i32>
> +   %extract = extractelement <2 x i32> %val.bc, i32 0
> +   store i32 %extract, i32 addrspace(1)* %out
> +  ret void
> +}
>
>
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