[PATCH] D17728: TableGen: Add hasNoSchedulingInfo flag to instructions
Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 1 12:07:53 PST 2016
This revision was automatically updated to reflect the committed changes.
Closed by commit rL262383: TableGen: Add hasNoSchedulingInfo to instructions (authored by matze).
Changed prior to commit:
http://reviews.llvm.org/D17728?vs=49398&id=49532#toc
Repository:
rL LLVM
http://reviews.llvm.org/D17728
Files:
llvm/trunk/include/llvm/Target/Target.td
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
Index: llvm/trunk/utils/TableGen/CodeGenInstruction.h
===================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h
@@ -257,6 +257,7 @@
bool isExtractSubreg : 1;
bool isInsertSubreg : 1;
bool isConvergent : 1;
+ bool hasNoSchedulingInfo : 1;
std::string DeprecatedReason;
bool HasComplexDeprecationPredicate;
Index: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
@@ -527,7 +527,8 @@
std::string InstName = Inst->TheDef->getName();
unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
if (!SCIdx) {
- dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
+ if (!Inst->hasNoSchedulingInfo)
+ dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
continue;
}
CodeGenSchedClass &SC = getSchedClass(SCIdx);
Index: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
===================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
@@ -324,6 +324,7 @@
isExtractSubreg = R->getValueAsBit("isExtractSubreg");
isInsertSubreg = R->getValueAsBit("isInsertSubreg");
isConvergent = R->getValueAsBit("isConvergent");
+ hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
bool Unset;
mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);
Index: llvm/trunk/include/llvm/Target/Target.td
===================================================================
--- llvm/trunk/include/llvm/Target/Target.td
+++ llvm/trunk/include/llvm/Target/Target.td
@@ -427,6 +427,11 @@
// Is this instruction a pseudo instruction for use by the assembler parser.
bit isAsmParserOnly = 0;
+ // This instruction is not expected to be queried for scheduling latencies
+ // and therefore needs no scheduling information even for a complete
+ // scheduling model.
+ bit hasNoSchedulingInfo = 0;
+
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
// Scheduling information from TargetSchedule.td.
@@ -765,7 +770,8 @@
// Standard Pseudo Instructions.
// This list must match TargetOpcodes.h and CodeGenTarget.cpp.
// Only these instructions are allowed in the TargetOpcode namespace.
-let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
+let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
+ Namespace = "TargetOpcode" in {
def PHI : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
@@ -857,6 +863,7 @@
let AsmString = "";
let hasSideEffects = 0;
let isAsCheapAsAMove = 1;
+ let hasNoSchedulingInfo = 0;
}
def BUNDLE : Instruction {
let OutOperandList = (outs);
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D17728.49532.patch
Type: text/x-patch
Size: 2983 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160301/96d74a27/attachment.bin>
More information about the llvm-commits
mailing list