[llvm] r262384 - TableGen: Check scheduling models for completeness
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 1 12:03:21 PST 2016
Author: matze
Date: Tue Mar 1 14:03:21 2016
New Revision: 262384
URL: http://llvm.org/viewvc/llvm-project?rev=262384&view=rev
Log:
TableGen: Check scheduling models for completeness
TableGen checks at compiletime that for scheduling models with
"CompleteModel = 1" one of the following holds:
- Is marked with the hasNoSchedulingInfo flag
- The instruction is a subclass of Sched
- There are InstRW definitions in the scheduling model
Typical steps necessary to complete a model:
- Ensure all pseudo instructions that are expanded before machine
scheduling (usually everything handled with EmitYYY() functions in
XXXTargetLowering).
- If a CPU does not support some instructions mark the corresponding
resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }".
- Add missing scheduling information.
Differential Revision: http://reviews.llvm.org/D17747
Modified:
llvm/trunk/include/llvm/Target/TargetSchedule.td
llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td
llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td
llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td
llvm/trunk/lib/Target/AMDGPU/SISchedule.td
llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td
llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td
llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td
llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
llvm/trunk/lib/Target/X86/X86Schedule.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
llvm/trunk/utils/TableGen/CodeGenSchedule.h
Modified: llvm/trunk/include/llvm/Target/TargetSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSchedule.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSchedule.td Tue Mar 1 14:03:21 2016
@@ -104,6 +104,7 @@ class SchedMachineModel {
def NoSchedModel : SchedMachineModel {
let NoModel = 1;
+ let CompleteModel = 0;
}
// Define a kind of processor resource that may be common across
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td Tue Mar 1 14:03:21 2016
@@ -26,6 +26,7 @@ def CortexA53Model : SchedMachineModel {
let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
// Specification - Instruction Timings"
// v 1.0 Spreadsheet
+ let CompleteModel = 0;
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td Tue Mar 1 14:03:21 2016
@@ -30,6 +30,7 @@ def CortexA57Model : SchedMachineModel {
// Enable partial & runtime unrolling. The magic number is chosen based on
// experiments and benchmarking data.
let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td Tue Mar 1 14:03:21 2016
@@ -17,6 +17,7 @@ def CycloneModel : SchedMachineModel {
let MicroOpBufferSize = 192; // Based on the reorder buffer.
let LoadLatency = 4; // Optimistic load latency.
let MispredictPenalty = 16; // 14-19 cycles are typical.
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td Tue Mar 1 14:03:21 2016
@@ -26,6 +26,7 @@ def KryoModel : SchedMachineModel {
// Enable partial & runtime unrolling. The magic number is chosen based on
// experiments and benchmarking data.
let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AMDGPU/SISchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SISchedule.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SISchedule.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SISchedule.td Tue Mar 1 14:03:21 2016
@@ -39,8 +39,12 @@ def Write64Bit : SchedWrite;
// instructions and have VALU rates, but write to the SALU (i.e. VOPC
// instructions)
-def SIFullSpeedModel : SchedMachineModel;
-def SIQuarterSpeedModel : SchedMachineModel;
+def SIFullSpeedModel : SchedMachineModel {
+ let CompleteModel = 0;
+}
+def SIQuarterSpeedModel : SchedMachineModel {
+ let CompleteModel = 0;
+}
// BufferSize = 0 means the processors are in-order.
let BufferSize = 0 in {
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Tue Mar 1 14:03:21 2016
@@ -1070,6 +1070,7 @@ def CortexA8Model : SchedMachineModel {
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let MispredictPenalty = 13; // Based on estimate of pipeline depth.
+ let CompleteModel = 0;
let Itineraries = CortexA8Itineraries;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td Tue Mar 1 14:03:21 2016
@@ -199,6 +199,7 @@ def HexagonModelV4 : SchedMachineModel {
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV4;
let LoadLatency = 1;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td Tue Mar 1 14:03:21 2016
@@ -163,6 +163,7 @@ def HexagonModelV55 : SchedMachineModel
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV55;
let LoadLatency = 1;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td Tue Mar 1 14:03:21 2016
@@ -303,6 +303,7 @@ def HexagonModelV60 : SchedMachineModel
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV60;
let LoadLatency = 1;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td Tue Mar 1 14:03:21 2016
@@ -13,7 +13,7 @@ def MipsP5600Model : SchedMachineModel {
int LoadLatency = 4;
int MispredictPenalty = 8; // TODO: Estimated
- let CompleteModel = 1;
+ let CompleteModel = 0;
}
let SchedModel = MipsP5600Model in {
Modified: llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSchedule440.td Tue Mar 1 14:03:21 2016
@@ -602,6 +602,8 @@ def PPC440Model : SchedMachineModel {
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
+ let CompleteModel = 0;
+
let Itineraries = PPC440Itineraries;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td Tue Mar 1 14:03:21 2016
@@ -166,6 +166,8 @@ def PPCA2Model : SchedMachineModel {
// Itineraries are queried instead.
let MispredictPenalty = 13;
+ let CompleteModel = 0;
+
let Itineraries = PPCA2Itineraries;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td Tue Mar 1 14:03:21 2016
@@ -316,5 +316,7 @@ def PPCE500mcModel : SchedMachineModel {
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
+ let CompleteModel = 0;
+
let Itineraries = PPCE500mcItineraries;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td Tue Mar 1 14:03:21 2016
@@ -376,5 +376,7 @@ def PPCE5500Model : SchedMachineModel {
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
+ let CompleteModel = 0;
+
let Itineraries = PPCE5500Itineraries;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleG5.td Tue Mar 1 14:03:21 2016
@@ -124,6 +124,8 @@ def G5Model : SchedMachineModel {
// Itineraries are queried instead.
let MispredictPenalty = 16;
+ let CompleteModel = 0;
+
let Itineraries = G5Itineraries;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td Tue Mar 1 14:03:21 2016
@@ -391,6 +391,8 @@ def P7Model : SchedMachineModel {
// Try to make sure we have at least 10 dispatch groups in a loop.
let LoopMicroOpBufferSize = 40;
+ let CompleteModel = 0;
+
let Itineraries = P7Itineraries;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td Tue Mar 1 14:03:21 2016
@@ -400,6 +400,8 @@ def P8Model : SchedMachineModel {
// Try to make sure we have at least 10 dispatch groups in a loop.
let LoopMicroOpBufferSize = 60;
+ let CompleteModel = 0;
+
let Itineraries = P8Itineraries;
}
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Tue Mar 1 14:03:21 2016
@@ -640,6 +640,7 @@ def GenericModel : SchedMachineModel {
let LoadLatency = 4;
let HighLatency = 10;
let PostRAScheduler = 0;
+ let CompleteModel = 0;
}
include "X86ScheduleAtom.td"
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Tue Mar 1 14:03:21 2016
@@ -544,6 +544,7 @@ def AtomModel : SchedMachineModel {
// simple loops, expand by a small factor to hide the backedge cost.
let LoopMicroOpBufferSize = 10;
let PostRAScheduler = 1;
+ let CompleteModel = 0;
let Itineraries = AtomItineraries;
}
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Tue Mar 1 14:03:21 2016
@@ -126,6 +126,8 @@ CodeGenSchedModels::CodeGenSchedModels(R
// Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and
// ProcResourceDefs.
collectProcResources();
+
+ checkCompleteness();
}
/// Gather all processor models.
@@ -1523,6 +1525,49 @@ void CodeGenSchedModels::collectProcReso
}
}
+void CodeGenSchedModels::checkCompleteness() {
+ bool Complete = true;
+ bool HadCompleteModel = false;
+ for (const CodeGenProcModel &ProcModel : procModels()) {
+ // Note that long-term we should check "CompleteModel", but for now most
+ // models that claim to be complete are actually not so we use a separate
+ // "CheckCompleteness" bit.
+ if (!ProcModel.ModelDef->getValueAsBit("CompleteModel"))
+ continue;
+ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+ if (Inst->hasNoSchedulingInfo)
+ continue;
+ unsigned SCIdx = getSchedClassIdx(*Inst);
+ if (!SCIdx) {
+ if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
+ PrintError("No schedule information for instruction '"
+ + Inst->TheDef->getName() + "'");
+ Complete = false;
+ }
+ continue;
+ }
+
+ const CodeGenSchedClass &SC = getSchedClass(SCIdx);
+ if (!SC.Writes.empty())
+ continue;
+
+ const RecVec &InstRWs = SC.InstRWs;
+ auto I = std::find_if(InstRWs.begin(), InstRWs.end(),
+ [&ProcModel] (const Record *R) {
+ return R->getValueAsDef("SchedModel") == ProcModel.ModelDef;
+ });
+ if (I == InstRWs.end()) {
+ PrintError("'" + ProcModel.ModelName + "' lacks information for '" +
+ Inst->TheDef->getName() + "'");
+ Complete = false;
+ }
+ }
+ HadCompleteModel = true;
+ }
+ if (!Complete)
+ PrintFatalError("Incomplete schedule model");
+}
+
// Collect itinerary class resources for each processor.
void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.h?rev=262384&r1=262383&r2=262384&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.h Tue Mar 1 14:03:21 2016
@@ -401,6 +401,8 @@ private:
void inferSchedClasses();
+ void checkCompleteness();
+
void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
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