[PATCH] D17747: TableGen: Check scheduling models for completeness

Tue Mar 1 11:34:16 PST 2016

MatzeB added a comment.

In http://reviews.llvm.org/D17747#365534, @atrick wrote:

> LGTM; Are they all really incomplete though once you add your hasNoSchedulingInfo flag?

Yes. My guess this is because

1. We currently only test completeness at runtime in assert builds but I don't think we test all the -mcpu=XXX variants that much in assert builds.
2. Things currently used as scheduling barriers are never queried (so don't fail on missing info)
3. Some instructions are not supported on every CPU in a target and have to be explicitely marked as unsupported.

Repository:
  rL LLVM

http://reviews.llvm.org/D17747