[PATCH] D17747: TableGen: Check scheduling models for completeness

Matthias Braun via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 1 11:28:22 PST 2016


MatzeB updated this revision to Diff 49517.
MatzeB added a comment.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: dsanders, arsenm.

New version which which does introduce the new CheckCompleteness flag anymore but uses the existing CompleteModel flag. Also sets CompleteModel = 0 on incomplete models (which is all of them).


Repository:
  rL LLVM

http://reviews.llvm.org/D17747

Files:
  include/llvm/Target/TargetSchedule.td
  lib/Target/AArch64/AArch64SchedA53.td
  lib/Target/AArch64/AArch64SchedA57.td
  lib/Target/AArch64/AArch64SchedCyclone.td
  lib/Target/AArch64/AArch64SchedKryo.td
  lib/Target/AMDGPU/SISchedule.td
  lib/Target/ARM/ARMScheduleA8.td
  lib/Target/Hexagon/HexagonScheduleV4.td
  lib/Target/Hexagon/HexagonScheduleV55.td
  lib/Target/Hexagon/HexagonScheduleV60.td
  lib/Target/Mips/MipsScheduleP5600.td
  lib/Target/PowerPC/PPCSchedule440.td
  lib/Target/PowerPC/PPCScheduleA2.td
  lib/Target/PowerPC/PPCScheduleE500mc.td
  lib/Target/PowerPC/PPCScheduleE5500.td
  lib/Target/PowerPC/PPCScheduleG5.td
  lib/Target/PowerPC/PPCScheduleP7.td
  lib/Target/PowerPC/PPCScheduleP8.td
  lib/Target/X86/X86Schedule.td
  lib/Target/X86/X86ScheduleAtom.td
  utils/TableGen/CodeGenSchedule.cpp
  utils/TableGen/CodeGenSchedule.h

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