[PATCH] D17041: [X86] Don't assume that a shuffle operand is #0: it isn't for VPERMV.

[Simon Pilgrim via llvm-commits]

RKSimon added a comment.

Some comments - might be void if altering the intrinsic argument ordering is going to happen.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:4908
@@ -4906,1 +4907,3 @@
 
+  assert(Ops.empty() && "Clear Ops vector before calling getTargetShuffleMask");
+
----------------
If you're going to add this maybe add an assertion for Mask.empty() as well?

================
Comment at: test/CodeGen/X86/avx2-vperm-combining.ll:3
@@ +2,3 @@
+; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s
+
+target triple = "x86_64-unknown-unknown"
----------------
Possibly rename this vector-shuffle-combining-avx2.ll ? It matches the other test files that have already been added for SSSE3/AVX-only shuffle intrinsic combine tests.

================
Comment at: test/CodeGen/X86/avx2-vperm-combining.ll:16
@@ +15,3 @@
+}
+
+declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>)
----------------
Add permps test as well.


http://reviews.llvm.org/D17041