[PATCH] D17728: TableGen: Add hasNoSchedulingInfo flag to instructions

[Matthias Braun via llvm-commits]

MatzeB created this revision.
MatzeB added a reviewer: atrick.
MatzeB added a subscriber: llvm-commits.
MatzeB set the repository for this revision to rL LLVM.
Herald added subscribers: mcrosier, MatzeB.

This introduces a new flag that indicates that a specific instruction will never be present when the MachineScheduler runs and therefore needs no scheduling information.

This is in preparation for an upcoming commit which checks completeness of a scheduling model when tablegen runs.

Repository:
  rL LLVM

http://reviews.llvm.org/D17728

Files:
  include/llvm/Target/Target.td
  utils/TableGen/CodeGenInstruction.cpp
  utils/TableGen/CodeGenInstruction.h
  utils/TableGen/CodeGenSchedule.cpp

Index: utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- utils/TableGen/CodeGenSchedule.cpp
+++ utils/TableGen/CodeGenSchedule.cpp
@@ -527,7 +527,8 @@
     std::string InstName = Inst->TheDef->getName();
     unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
     if (!SCIdx) {
-      dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
+      if (!Inst->hasNoSchedulingInfo)
+        dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
       continue;
     }
     CodeGenSchedClass &SC = getSchedClass(SCIdx);
Index: utils/TableGen/CodeGenInstruction.h
===================================================================
--- utils/TableGen/CodeGenInstruction.h
+++ utils/TableGen/CodeGenInstruction.h
@@ -257,6 +257,7 @@
     bool isExtractSubreg : 1;
     bool isInsertSubreg : 1;
     bool isConvergent : 1;
+    bool hasNoSchedulingInfo : 1;
 
     std::string DeprecatedReason;
     bool HasComplexDeprecationPredicate;
Index: utils/TableGen/CodeGenInstruction.cpp
===================================================================
--- utils/TableGen/CodeGenInstruction.cpp
+++ utils/TableGen/CodeGenInstruction.cpp
@@ -324,6 +324,7 @@
   isExtractSubreg = R->getValueAsBit("isExtractSubreg");
   isInsertSubreg = R->getValueAsBit("isInsertSubreg");
   isConvergent = R->getValueAsBit("isConvergent");
+  hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
 
   bool Unset;
   mayLoad      = R->getValueAsBitOrUnset("mayLoad", Unset);
Index: include/llvm/Target/Target.td
===================================================================
--- include/llvm/Target/Target.td
+++ include/llvm/Target/Target.td
@@ -427,6 +427,11 @@
   // Is this instruction a pseudo instruction for use by the assembler parser.
   bit isAsmParserOnly = 0;
 
+  // This instruction is not expected to be queried for scheduling latencies
+  // and therefore needs no scheduling information even for a complete
+  // scheduling model.
+  bit hasNoSchedulingInfo = 0;
+
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
   // Scheduling information from TargetSchedule.td.
@@ -765,7 +770,8 @@
 // Standard Pseudo Instructions.
 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
 // Only these instructions are allowed in the TargetOpcode namespace.
-let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
+let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
+    Namespace = "TargetOpcode" in {
 def PHI : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
@@ -857,6 +863,7 @@
   let AsmString = "";
   let hasSideEffects = 0;
   let isAsCheapAsAMove = 1;
+  let hasNoSchedulingInfo = 0;
 }
 def BUNDLE : Instruction {
   let OutOperandList = (outs);


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