[PATCH] D17661: [AArch64] Add MMOs to callee-save load/store instructions.

[Geoff Berry via llvm-commits]

gberry updated this revision to Diff 49399.
gberry added a comment.

Add potential test case.


http://reviews.llvm.org/D17661

Files:
  lib/Target/AArch64/AArch64FrameLowering.cpp
  test/CodeGen/AArch64/arm64-csldst-mmo.ll

Index: test/CodeGen/AArch64/arm64-csldst-mmo.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/arm64-csldst-mmo.ll
@@ -0,0 +1,19 @@
+; REQUIRES: asserts
+;
+; Verify that MMOs are added to callee-save save/restore instructions.
+;
+; RUN: llc < %s -mtriple=arm64-linux-gnu -print-after=prologepilog -o - 2>&1 > /dev/null | FileCheck %s
+; CHECK: STRXpre %X{{[0-9]+}}<{{[a-zA-Z0-9]+}}>, %SP<{{[a-zA-Z0-9]+}}>, -{{[0-9]+}}; flags: FrameSetup mem:ST8[FixedStack2]
+; CHECK: STPXi %FP<{{[a-zA-Z0-9]*}}>, %LR<{{[a-zA-Z0-9]*}}>, %SP, {{[0-9]+}}; flags: FrameSetup mem:ST8[FixedStack1] ST8[FixedStack0]
+; CHECK: LDPXi %SP, {{[0-9]+}}; flags: FrameDestroy mem:LD8[FixedStack1] LD8[FixedStack0]
+; CHECK: LDRXpost %SP<{{[a-zA-Z0-9]*}}>, {{[0-9]+}}; flags: FrameDestroy mem:LD8[FixedStack2]
+
+declare i32 @bar()
+
+define i32 @foo() {
+entry:
+  %tmp1 = call i32 @bar()
+  %tmp2 = call i32 @bar()
+  %tmp3 = add i32 %tmp1, %tmp2
+  ret i32 %tmp3
+}
Index: lib/Target/AArch64/AArch64FrameLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64FrameLowering.cpp
+++ lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -858,13 +858,19 @@
         .addReg(AArch64::SP)
         .addImm(Offset) // [sp, #offset * 8], where factor * 8 is implicit
         .setMIFlag(MachineInstr::FrameSetup);
+      MIB.addMemOperand(MF.getMachineMemOperand(
+          MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
+          MachineMemOperand::MOStore, 8, 8));
     } else {
       MBB.addLiveIn(Reg1);
       MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))
         .addReg(AArch64::SP)
         .addImm(BumpSP ? Offset * 8 : Offset) // pre-inc version is unscaled
         .setMIFlag(MachineInstr::FrameSetup);
     }
+    MIB.addMemOperand(MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
+        MachineMemOperand::MOStore, 8, 8));
   }
   return true;
 }
@@ -922,18 +928,25 @@
     if (BumpSP)
       MIB.addReg(AArch64::SP, RegState::Define);
 
-    if (RPI.isPaired())
+    if (RPI.isPaired()) {
       MIB.addReg(Reg2, getDefRegState(true))
         .addReg(Reg1, getDefRegState(true))
         .addReg(AArch64::SP)
         .addImm(Offset) // [sp], #offset * 8  or [sp, #offset * 8]
                         // where the factor * 8 is implicit
         .setMIFlag(MachineInstr::FrameDestroy);
-    else
+      MIB.addMemOperand(MF.getMachineMemOperand(
+          MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
+          MachineMemOperand::MOLoad, 8, 8));
+    } else {
       MIB.addReg(Reg1, getDefRegState(true))
         .addReg(AArch64::SP)
         .addImm(BumpSP ? Offset * 8 : Offset) // post-dec version is unscaled
         .setMIFlag(MachineInstr::FrameDestroy);
+    }
+    MIB.addMemOperand(MF.getMachineMemOperand(
+        MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
+        MachineMemOperand::MOLoad, 8, 8));
   }
   return true;
 }


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