[PATCH] D17691: [X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG

[Simon Pilgrim via llvm-commits]

RKSimon added a comment.

Created PR26762 to investigate the issue with bitcasts preventing masked instruction combining


Repository:
  rL LLVM

http://reviews.llvm.org/D17691