[PATCH] D17691: [X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG

[Simon Pilgrim via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: igorb, delena, congh, spatel.
RKSimon added a subscriber: llvm-commits.
RKSimon set the repository for this revision to rL LLVM.

Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns.

This won't solve the issues with PR25718 (load+zext 8xi8 to 8xi32) but is one of several things that needs to be done at the same time.

Igor/Elena - can you advise why the masks aren't being folded into the VPMOVZX instructions on skylake targets any more please?


Repository:
  rL LLVM

http://reviews.llvm.org/D17691

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx512-ext.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-zext.ll

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