[PATCH] D17615: Fix Sparc 32bit Lowering to rebundle up v2i32 values.

[Nirav Dave via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL262048: Fix Sparc 32bit Lowering to rebundle up v2i32 values. (authored by niravd).

Changed prior to commit:
  http://reviews.llvm.org/D17615?vs=49207&id=49210#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D17615

Files:
  llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/trunk/test/CodeGen/SPARC/vector-call.ll

Index: llvm/trunk/test/CodeGen/SPARC/vector-call.ll
===================================================================
--- llvm/trunk/test/CodeGen/SPARC/vector-call.ll
+++ llvm/trunk/test/CodeGen/SPARC/vector-call.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=sparc | FileCheck %s
+
+; Verify that we correctly handle vector types that appear directly
+; during call lowering. These may cause issue as v2i32 is a legal type
+; for the implementation of LDD
+
+; CHECK-LABEL: fun16v:
+; CHECK: foo1_16v
+; CHECK: foo2_16v
+
+define <2 x i16> @fun16v() #0 {
+  %1 = tail call <2 x i16> @foo1_16v()
+  %2 = tail call <2 x i16> @foo2_16v()
+  %3 = and <2 x i16> %2, %1
+  ret <2 x i16> %3
+}
+
+declare <2 x i16> @foo1_16v() #0
+declare <2 x i16> @foo2_16v() #0
+
+; CHECK-LABEL: fun32v:
+; CHECK: foo1_32v
+; CHECK: foo2_32v
+
+define <2 x i32> @fun32v() #0 {
+  %1 = tail call <2 x i32> @foo1_32v()
+  %2 = tail call <2 x i32> @foo2_32v()
+  %3 = and <2 x i32> %2, %1
+  ret <2 x i32> %3
+}
+
+declare <2 x i32> @foo1_32v() #0
+declare <2 x i32> @foo2_32v() #0
Index: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
@@ -999,10 +999,29 @@
 
   // Copy all of the result registers out of their specified physreg.
   for (unsigned i = 0; i != RVLocs.size(); ++i) {
-    Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
-                               RVLocs[i].getValVT(), InFlag).getValue(1);
-    InFlag = Chain.getValue(2);
-    InVals.push_back(Chain.getValue(0));
+    if (RVLocs[i].getLocVT() == MVT::v2i32) {
+      SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
+      SDValue Lo = DAG.getCopyFromReg(
+          Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
+      Chain = Lo.getValue(1);
+      InFlag = Lo.getValue(2);
+      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
+                        DAG.getConstant(0, dl, MVT::i32));
+      SDValue Hi = DAG.getCopyFromReg(
+          Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
+      Chain = Hi.getValue(1);
+      InFlag = Hi.getValue(2);
+      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
+                        DAG.getConstant(1, dl, MVT::i32));
+      InVals.push_back(Vec);
+    } else {
+      Chain =
+          DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
+                             RVLocs[i].getValVT(), InFlag)
+              .getValue(1);
+      InFlag = Chain.getValue(2);
+      InVals.push_back(Chain.getValue(0));
+    }
   }
 
   return Chain;


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