[PATCH] D17647: Legalize FNEG on PPC when possible

[amehsan via llvm-commits]

amehsan created this revision.
amehsan added reviewers: kbarton, nemanjai.
amehsan added a subscriber: llvm-commits.

Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode

http://reviews.llvm.org/D17647

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp
  test/CodeGen/PowerPC/vec_fneg.ll

Index: test/CodeGen/PowerPC/vec_fneg.ll
===================================================================
--- test/CodeGen/PowerPC/vec_fneg.ll
+++ test/CodeGen/PowerPC/vec_fneg.ll
@@ -1,8 +1,37 @@
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s -check-prefix=CHECK-NOVSX
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=+vsx |  FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=-vsx |  FileCheck %s \
+; RUN:          -check-prefix=CHECK-NOVSX
 
-define void @t(<4 x float>* %A) {
+define void @test_float(<4 x float>* %A) {
+; CHECK-LABEL: test_float
+; CHECK-NOVSX-LABEL: test_float
 	%tmp2 = load <4 x float>, <4 x float>* %A
 	%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
 	store <4 x float> %tmp3, <4 x float>* %A
 	ret void
+
+; CHECK: xvnegsp
+; CHECK: blr
+; CHECK-NOVSX: vsubfp
+; CHECK-NOVSX: blr
+
+}
+
+define void @test_double(<2 x double>* %A) {
+; CHECK-LABEL: test_double
+; CHECK-NOVSX-LABEL: test_double
+	%tmp2 = load <2 x double>, <2 x double>* %A
+	%tmp3 = fsub <2 x double> < double -0.000000e+00, double -0.000000e+00 >, %tmp2
+	store <2 x double> %tmp3, <2 x double>* %A
+	ret void
+
+; CHECK: xvnegdp
+; CHECK: blr
+; CHECK-NOVSX: fneg
+; CHECK-NOVSX: fneg
+; CHECK-NOVSX: blr
+
 }
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -647,6 +647,9 @@
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
 
+      setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
+      setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
+
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
     }
 


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