[PATCH] D17540: [MIPS][LLVM-MC] Fix Disassemble of Negative Offset

[Nitesh Jain via llvm-commits]

nitesh.jain created this revision.
nitesh.jain added a reviewer: dsanders.
nitesh.jain added subscribers: jaydeep, bhushan, sagar, mohit.bhakkad, llvm-commits.
nitesh.jain set the repository for this revision to rL LLVM.
Herald added a reviewer: vkalintiris.
Herald added a subscriber: dsanders.

The type of Imm in MipsDisassembler.cpp was incorrect  since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset  is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added.

Repository:
  rL LLVM

http://reviews.llvm.org/D17540

Files:
  lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
  test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
  test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
  test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
  test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt

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