[llvm] r261621 - [AMDGPU] Fix operands of S_BFE_U64 and S_BFM_B64

[Nikolay Haustov via llvm-commits]

Author: nhaustov
Date: Tue Feb 23 03:19:14 2016
New Revision: 261621

URL: http://llvm.org/viewvc/llvm-project?rev=261621&view=rev
Log:
[AMDGPU] Fix operands of S_BFE_U64 and S_BFM_B64

src1 of s_bfe_u64 is 32-bit (same as s_bfe_i64).
src0 and src1 of s_bfm_b64 are 32-bit.
Update tests.

Review: http://reviews.llvm.org/D17480

Reviewers: arsenm

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
    llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
    llvm/trunk/test/MC/AMDGPU/sop2.s

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=261621&r1=261620&r2=261621&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Tue Feb 23 03:19:14 2016
@@ -861,6 +861,11 @@ multiclass SOP2_64_32 <sop2 op, string o
     opName#" $dst, $src0, $src1", pattern
 >;
 
+multiclass SOP2_64_32_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
+    op, opName, (outs SReg_64:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
+    opName#" $dst, $src0, $src1", pattern
+>;
+
 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
                     string opName, PatLeaf cond> : SOPC <
   op, (outs), (ins rc:$src0, rc:$src1),

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=261621&r1=261620&r2=261621&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Tue Feb 23 03:19:14 2016
@@ -307,7 +307,7 @@ defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23,
 
 defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32",
   [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
-defm S_BFM_B64 : SOP2_64 <sop2<0x25, 0x23>, "s_bfm_b64", []>;
+defm S_BFM_B64 : SOP2_64_32_32 <sop2<0x25, 0x23>, "s_bfm_b64", []>;
 defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
   [(set i32:$dst, (mul i32:$src0, i32:$src1))]
 >;
@@ -317,7 +317,7 @@ defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x2
 let Defs = [SCC] in {
 defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>;
 defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>;
-defm S_BFE_U64 : SOP2_64 <sop2<0x29, 0x27>, "s_bfe_u64", []>;
+defm S_BFE_U64 : SOP2_64_32 <sop2<0x29, 0x27>, "s_bfe_u64", []>;
 defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>;
 } // End Defs = [SCC]
 

Modified: llvm/trunk/test/MC/AMDGPU/sop2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sop2.s?rev=261621&r1=261620&r2=261621&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sop2.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sop2.s Tue Feb 23 03:19:14 2016
@@ -106,8 +106,8 @@ s_ashr_i64 s[2:3], s[4:5], s6
 // CHECK: s_bfm_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
 s_bfm_b32 s2, s4, s6
 
-// CHECK: s_bfm_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x92]
-s_bfm_b64 s[2:3], s[4:5], s[6:7]
+// CHECK: s_bfm_b64 s[2:3], s4, s6 ; encoding: [0x04,0x06,0x82,0x92]
+s_bfm_b64 s[2:3], s4, s6
 
 // CHECK: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x93]
 s_mul_i32 s2, s4, s6
@@ -118,8 +118,8 @@ s_bfe_u32 s2, s4, s6
 // CHECK: s_bfe_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x94]
 s_bfe_i32 s2, s4, s6
 
-// CHECK: s_bfe_u64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x94]
-s_bfe_u64 s[2:3], s[4:5], s[6:7]
+// CHECK: s_bfe_u64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x94]
+s_bfe_u64 s[2:3], s[4:5], s6
 
 // CHECK: s_bfe_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x02,0x95]
 s_bfe_i64 s[2:3], s[4:5], s6