[llvm] r261529 - [mips] added support for trunc macro
Zoran Jovanovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 22 08:00:26 PST 2016
Author: zjovanovic
Date: Mon Feb 22 10:00:23 2016
New Revision: 261529
URL: http://llvm.org/viewvc/llvm-project?rev=261529&view=rev
Log:
[mips] added support for trunc macro
Author: obucina
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D15745
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Feb 22 10:00:23 2016
@@ -220,6 +220,9 @@ class MipsAsmParser : public MCTargetAsm
SmallVectorImpl<MCInst> &Instructions, const bool IsMips64,
const bool Signed);
+ bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
+ SmallVectorImpl<MCInst> &Instructions);
+
bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
@@ -2054,6 +2057,15 @@ MipsAsmParser::tryExpandInstruction(MCIn
case Mips::DUDivMacro:
return expandDiv(Inst, IDLoc, Instructions, true, false) ? MER_Fail
: MER_Success;
+ case Mips::PseudoTRUNC_W_S:
+ return expandTrunc(Inst, false, false, IDLoc, Instructions) ? MER_Fail
+ : MER_Success;
+ case Mips::PseudoTRUNC_W_D32:
+ return expandTrunc(Inst, true, false, IDLoc, Instructions) ? MER_Fail
+ : MER_Success;
+ case Mips::PseudoTRUNC_W_D:
+ return expandTrunc(Inst, true, true, IDLoc, Instructions) ? MER_Fail
+ : MER_Success;
case Mips::Ulh:
return expandUlh(Inst, true, IDLoc, Instructions) ? MER_Fail : MER_Success;
case Mips::Ulhu:
@@ -3057,6 +3069,44 @@ bool MipsAsmParser::expandDiv(MCInst &In
return false;
}
+bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
+ SMLoc IDLoc,
+ SmallVectorImpl<MCInst> &Instructions) {
+
+ assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+ assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
+ Inst.getOperand(2).isReg() && "Invalid instruction operand.");
+
+ unsigned FirstReg = Inst.getOperand(0).getReg();
+ unsigned SecondReg = Inst.getOperand(1).getReg();
+ unsigned ThirdReg = Inst.getOperand(2).getReg();
+
+ if (hasMips1() && !hasMips2()) {
+ unsigned ATReg = getATReg(IDLoc);
+ if (!ATReg)
+ return true;
+ emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Instructions);
+ emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Instructions);
+ createNop(false, IDLoc, Instructions);
+ emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, Instructions);
+ emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, Instructions);
+ emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, Instructions);
+ createNop(false, IDLoc, Instructions);
+ emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
+ : Mips::CVT_W_S,
+ FirstReg, SecondReg, IDLoc, Instructions);
+ emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, Instructions);
+ createNop(false, IDLoc, Instructions);
+ return false;
+ }
+
+ emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
+ : Mips::TRUNC_W_S,
+ FirstReg, SecondReg, IDLoc, Instructions);
+
+ return false;
+}
+
bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
if (hasMips32r6() || hasMips64r6()) {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Feb 22 10:00:23 2016
@@ -551,6 +551,20 @@ class ExtractElementF64Base<RegisterOper
def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
+def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
+ (ins FGR32Opnd:$fs, GPR32Opnd:$rs),
+ "trunc.w.s\t$fd, $fs, $rs">;
+
+def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
+ (ins AFGR64Opnd:$fs, GPR32Opnd:$rs),
+ "trunc.w.d\t$fd, $fs, $rs">,
+ FGR_32, HARDFLOAT;
+
+def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
+ (ins FGR64Opnd:$fs, GPR32Opnd:$rs),
+ "trunc.w.d\t$fd, $fs, $rs">,
+ FGR_64, HARDFLOAT;
+
//===----------------------------------------------------------------------===//
// InstAliases.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Mon Feb 22 10:00:23 2016
@@ -124,4 +124,29 @@ a:
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
+ .set at
+ trunc.w.s $f4,$f6,$4
+ # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
+ # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
+ # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+ # CHECK: ori $1, $4, 3 # encoding: [0x34,0x81,0x00,0x03]
+ # CHECK: xori $1, $1, 2 # encoding: [0x38,0x21,0x00,0x02]
+ # CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
+ # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+ # CHECK: cvt.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x24]
+ # CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
+ # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+
+ trunc.w.d $f4,$f6,$4
+ # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
+ # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
+ # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+ # CHECK: ori $1, $4, 3 # encoding: [0x34,0x81,0x00,0x03]
+ # CHECK: xori $1, $1, 2 # encoding: [0x38,0x21,0x00,0x02]
+ # CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
+ # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+ # CHECK: cvt.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x24]
+ # CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
+ # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+
1:
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Mon Feb 22 10:00:23 2016
@@ -168,8 +168,10 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Mon Feb 22 10:00:23 2016
@@ -232,10 +232,12 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.l.d $f23,$f23
- trunc.l.s $f28,$f31
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
+ trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Mon Feb 22 10:00:23 2016
@@ -198,8 +198,10 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Mon Feb 22 10:00:23 2016
@@ -235,8 +235,10 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Mon Feb 22 10:00:23 2016
@@ -235,8 +235,10 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Mon Feb 22 10:00:23 2016
@@ -236,8 +236,10 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Mon Feb 22 10:00:23 2016
@@ -261,10 +261,12 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.l.d $f23,$f23
- trunc.l.s $f28,$f31
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
+ trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Mon Feb 22 10:00:23 2016
@@ -263,10 +263,12 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.l.d $f23,$f23
- trunc.l.s $f28,$f31
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
+ trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Mon Feb 22 10:00:23 2016
@@ -282,10 +282,12 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.l.d $f23,$f23
- trunc.l.s $f28,$f31
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
+ trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Mon Feb 22 10:00:23 2016
@@ -308,10 +308,12 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.l.d $f23,$f23
- trunc.l.s $f28,$f31
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
+ trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Mon Feb 22 10:00:23 2016
@@ -308,10 +308,12 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.l.d $f23,$f23
- trunc.l.s $f28,$f31
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
+ trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=261529&r1=261528&r2=261529&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Mon Feb 22 10:00:23 2016
@@ -309,10 +309,12 @@ a:
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647
- trunc.l.d $f23,$f23
- trunc.l.s $f28,$f31
- trunc.w.d $f22,$f15
- trunc.w.s $f28,$f30
+ trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
+ trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
+ trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
+ trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
+ trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
+ trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
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