[llvm] r261520 - AVX512: Fix scalar mem operands.
Igor Breger via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 22 03:48:28 PST 2016
Author: ibreger
Date: Mon Feb 22 05:48:27 2016
New Revision: 261520
URL: http://llvm.org/viewvc/llvm-project?rev=261520&view=rev
Log:
AVX512: Fix scalar mem operands.
Differential Revision: http://reviews.llvm.org/D17500
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/MC/X86/avx512-encodings.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=261520&r1=261519&r2=261520&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Mon Feb 22 05:48:27 2016
@@ -1414,7 +1414,7 @@ multiclass avx512_cmp_scalar<X86VectorVT
let mayLoad = 1 in
defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
(outs _.KRC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
+ (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
"vcmp${cc}"#_.Suffix,
"$src2, $src1", "$src1, $src2",
(OpNode (_.VT _.RC:$src1),
@@ -1439,7 +1439,7 @@ multiclass avx512_cmp_scalar<X86VectorVT
"$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
(outs _.KRC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
+ (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
"vcmp"#_.Suffix,
"$cc, $src2, $src1", "$src1, $src2, $cc">,
EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
@@ -3616,7 +3616,7 @@ multiclass avx512_fp_scalar<bits<8> opc,
itins.rr, IsCommutable>;
defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+ (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2",
(VecNode (_.VT _.RC:$src1),
(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
@@ -3821,9 +3821,11 @@ multiclass avx512_fp_scalef_scalar<bits<
(_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
let mayLoad = 1 in {
defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
+ (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
"$src2, $src1", "$src1, $src2",
- (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
+ (OpNode _.RC:$src1,
+ (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
+ (i32 FROUND_CURRENT))>;
}//let mayLoad = 1
}
@@ -4691,7 +4693,7 @@ multiclass avx512_fma3s_common<bits<8> o
let mayLoad = 1 in
defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
+ (ins _.RC:$src2, _.ScalarMemOp:$src3), OpcodeStr,
"$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
@@ -5035,7 +5037,7 @@ let Predicates = [HasAVX512] in {
def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
!strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
[]>, EVEX, EVEX_B;
- def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
+ def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
EVEX;
@@ -5109,7 +5111,7 @@ multiclass avx512_cvt_fp_scalar<bits<8>
(_Src.VT _Src.RC:$src2)))>,
EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
+ (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2",
(_.VT (OpNode (_Src.VT _Src.RC:$src1),
(_Src.VT (scalar_to_vector
@@ -5206,7 +5208,7 @@ multiclass avx512_vcvt_fp<bits<8> opc, s
(bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _Src.MemOp:$src), OpcodeStr,
+ (ins _Src.ScalarMemOp:$src), OpcodeStr,
"${src}"##Broadcast, "${src}"##Broadcast,
(_.VT (OpNode (_Src.VT
(X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
@@ -5739,7 +5741,7 @@ multiclass avx512_fp14_s<bits<8> opc, st
(OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
let mayLoad = 1 in {
defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+ (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2",
(OpNode (_.VT _.RC:$src1),
(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
@@ -5819,7 +5821,7 @@ multiclass avx512_fp28_s<bits<8> opc, st
(i32 FROUND_NO_EXC))>, EVEX_B;
defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+ (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2",
(OpNode (_.VT _.RC:$src1),
(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
@@ -5855,7 +5857,7 @@ multiclass avx512_fp28_p<bits<8> opc, st
(i32 FROUND_CURRENT))>;
defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.MemOp:$src), OpcodeStr,
+ (ins _.ScalarMemOp:$src), OpcodeStr,
"${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
(OpNode (_.FloatVT
(X86VBroadcast (_.ScalarLdFrag addr:$src))),
@@ -5973,7 +5975,7 @@ multiclass avx512_sqrt_scalar<bits<8> op
(i32 FROUND_CURRENT))>;
let mayLoad = 1 in
defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+ (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
"$src2, $src1", "$src1, $src2",
(OpNodeRnd (_.VT _.RC:$src1),
(_.VT (scalar_to_vector
@@ -6051,7 +6053,8 @@ avx512_rndscale_scalar<bits<8> opc, stri
let mayLoad = 1 in
defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
+ (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
+ OpcodeStr,
"$src3, $src2, $src1", "$src1, $src2, $src3",
(_.VT (X86RndScales (_.VT _.RC:$src1),
(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
Modified: llvm/trunk/test/MC/X86/avx512-encodings.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/avx512-encodings.s?rev=261520&r1=261519&r2=261520&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/avx512-encodings.s (original)
+++ llvm/trunk/test/MC/X86/avx512-encodings.s Mon Feb 22 05:48:27 2016
@@ -6416,29 +6416,29 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
// CHECK: encoding: [0x62,0xb1,0x56,0x78,0x58,0xfb]
vaddss {rz-sae}, %xmm19, %xmm5, %xmm7
-// CHECK: vaddss (%rcx), %xmm5, %xmm7
-// CHECK: encoding: [0x62,0xf1,0x56,0x08,0x58,0x39]
- vaddss (%rcx), %xmm5, %xmm7
-
-// CHECK: vaddss 291(%rax,%r14,8), %xmm5, %xmm7
-// CHECK: encoding: [0x62,0xb1,0x56,0x08,0x58,0xbc,0xf0,0x23,0x01,0x00,0x00]
- vaddss 291(%rax,%r14,8), %xmm5, %xmm7
-
-// CHECK: vaddss 508(%rdx), %xmm5, %xmm7
-// CHECK: encoding: [0x62,0xf1,0x56,0x08,0x58,0x7a,0x7f]
- vaddss 508(%rdx), %xmm5, %xmm7
-
-// CHECK: vaddss 512(%rdx), %xmm5, %xmm7
-// CHECK: encoding: [0x62,0xf1,0x56,0x08,0x58,0xba,0x00,0x02,0x00,0x00]
- vaddss 512(%rdx), %xmm5, %xmm7
-
-// CHECK: vaddss -512(%rdx), %xmm5, %xmm7
-// CHECK: encoding: [0x62,0xf1,0x56,0x08,0x58,0x7a,0x80]
- vaddss -512(%rdx), %xmm5, %xmm7
-
-// CHECK: vaddss -516(%rdx), %xmm5, %xmm7
-// CHECK: encoding: [0x62,0xf1,0x56,0x08,0x58,0xba,0xfc,0xfd,0xff,0xff]
- vaddss -516(%rdx), %xmm5, %xmm7
+// CHECK: vaddss (%rcx), %xmm25, %xmm7
+// CHECK: encoding: [0x62,0xf1,0x36,0x00,0x58,0x39]
+ vaddss (%rcx), %xmm25, %xmm7
+
+// CHECK: vaddss 291(%rax,%r14,8), %xmm25, %xmm7
+// CHECK: encoding: [0x62,0xb1,0x36,0x00,0x58,0xbc,0xf0,0x23,0x01,0x00,0x00]
+ vaddss 291(%rax,%r14,8), %xmm25, %xmm7
+
+// CHECK: vaddss 508(%rdx), %xmm25, %xmm7
+// CHECK: encoding: [0x62,0xf1,0x36,0x00,0x58,0x7a,0x7f]
+ vaddss 508(%rdx), %xmm25, %xmm7
+
+// CHECK: vaddss 512(%rdx), %xmm25, %xmm7
+// CHECK: encoding: [0x62,0xf1,0x36,0x00,0x58,0xba,0x00,0x02,0x00,0x00]
+ vaddss 512(%rdx), %xmm25, %xmm7
+
+// CHECK: vaddss -512(%rdx), %xmm25, %xmm7
+// CHECK: encoding: [0x62,0xf1,0x36,0x00,0x58,0x7a,0x80]
+ vaddss -512(%rdx), %xmm25, %xmm7
+
+// CHECK: vaddss -516(%rdx), %xmm25, %xmm7
+// CHECK: encoding: [0x62,0xf1,0x36,0x00,0x58,0xba,0xfc,0xfd,0xff,0xff]
+ vaddss -516(%rdx), %xmm25, %xmm7
// CHECK: vdivpd {rn-sae}, %zmm11, %zmm6, %zmm18
// CHECK: encoding: [0x62,0xc1,0xcd,0x18,0x5e,0xd3]
@@ -6640,29 +6640,29 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
// CHECK: encoding: [0x62,0x71,0x5e,0x18,0x5f,0xc6]
vmaxss {sae}, %xmm6, %xmm4, %xmm8
-// CHECK: vmaxss (%rcx), %xmm4, %xmm8
-// CHECK: encoding: [0x62,0x71,0x5e,0x08,0x5f,0x01]
- vmaxss (%rcx), %xmm4, %xmm8
-
-// CHECK: vmaxss 291(%rax,%r14,8), %xmm4, %xmm8
-// CHECK: encoding: [0x62,0x31,0x5e,0x08,0x5f,0x84,0xf0,0x23,0x01,0x00,0x00]
- vmaxss 291(%rax,%r14,8), %xmm4, %xmm8
-
-// CHECK: vmaxss 508(%rdx), %xmm4, %xmm8
-// CHECK: encoding: [0x62,0x71,0x5e,0x08,0x5f,0x42,0x7f]
- vmaxss 508(%rdx), %xmm4, %xmm8
-
-// CHECK: vmaxss 512(%rdx), %xmm4, %xmm8
-// CHECK: encoding: [0x62,0x71,0x5e,0x08,0x5f,0x82,0x00,0x02,0x00,0x00]
- vmaxss 512(%rdx), %xmm4, %xmm8
-
-// CHECK: vmaxss -512(%rdx), %xmm4, %xmm8
-// CHECK: encoding: [0x62,0x71,0x5e,0x08,0x5f,0x42,0x80]
- vmaxss -512(%rdx), %xmm4, %xmm8
-
-// CHECK: vmaxss -516(%rdx), %xmm4, %xmm8
-// CHECK: encoding: [0x62,0x71,0x5e,0x08,0x5f,0x82,0xfc,0xfd,0xff,0xff]
- vmaxss -516(%rdx), %xmm4, %xmm8
+// CHECK: vmaxss (%rcx), %xmm4, %xmm18
+// CHECK: encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x11]
+ vmaxss (%rcx), %xmm4, %xmm18
+
+// CHECK: vmaxss 291(%rax,%r14,8), %xmm4, %xmm18
+// CHECK: encoding: [0x62,0xa1,0x5e,0x08,0x5f,0x94,0xf0,0x23,0x01,0x00,0x00]
+ vmaxss 291(%rax,%r14,8), %xmm4, %xmm18
+
+// CHECK: vmaxss 508(%rdx), %xmm4, %xmm18
+// CHECK: encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x52,0x7f]
+ vmaxss 508(%rdx), %xmm4, %xmm18
+
+// CHECK: vmaxss 512(%rdx), %xmm4, %xmm18
+// CHECK: encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x92,0x00,0x02,0x00,0x00]
+ vmaxss 512(%rdx), %xmm4, %xmm18
+
+// CHECK: vmaxss -512(%rdx), %xmm4, %xmm18
+// CHECK: encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x52,0x80]
+ vmaxss -512(%rdx), %xmm4, %xmm18
+
+// CHECK: vmaxss -516(%rdx), %xmm4, %xmm18
+// CHECK: encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x92,0xfc,0xfd,0xff,0xff]
+ vmaxss -516(%rdx), %xmm4, %xmm18
// CHECK: vminpd {sae}, %zmm22, %zmm6, %zmm6
// CHECK: encoding: [0x62,0xb1,0xcd,0x18,0x5d,0xf6]
@@ -6812,29 +6812,29 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
// CHECK: encoding: [0x62,0x31,0xdf,0x78,0x59,0xea]
vmulsd {rz-sae}, %xmm18, %xmm4, %xmm13
-// CHECK: vmulsd (%rcx), %xmm4, %xmm13
-// CHECK: encoding: [0x62,0x71,0xdf,0x08,0x59,0x29]
- vmulsd (%rcx), %xmm4, %xmm13
-
-// CHECK: vmulsd 291(%rax,%r14,8), %xmm4, %xmm13
-// CHECK: encoding: [0x62,0x31,0xdf,0x08,0x59,0xac,0xf0,0x23,0x01,0x00,0x00]
- vmulsd 291(%rax,%r14,8), %xmm4, %xmm13
-
-// CHECK: vmulsd 1016(%rdx), %xmm4, %xmm13
-// CHECK: encoding: [0x62,0x71,0xdf,0x08,0x59,0x6a,0x7f]
- vmulsd 1016(%rdx), %xmm4, %xmm13
-
-// CHECK: vmulsd 1024(%rdx), %xmm4, %xmm13
-// CHECK: encoding: [0x62,0x71,0xdf,0x08,0x59,0xaa,0x00,0x04,0x00,0x00]
- vmulsd 1024(%rdx), %xmm4, %xmm13
-
-// CHECK: vmulsd -1024(%rdx), %xmm4, %xmm13
-// CHECK: encoding: [0x62,0x71,0xdf,0x08,0x59,0x6a,0x80]
- vmulsd -1024(%rdx), %xmm4, %xmm13
-
-// CHECK: vmulsd -1032(%rdx), %xmm4, %xmm13
-// CHECK: encoding: [0x62,0x71,0xdf,0x08,0x59,0xaa,0xf8,0xfb,0xff,0xff]
- vmulsd -1032(%rdx), %xmm4, %xmm13
+// CHECK: vmulsd (%rcx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0x39]
+ vmulsd (%rcx), %xmm4, %xmm23
+
+// CHECK: vmulsd 291(%rax,%r14,8), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xa1,0xdf,0x08,0x59,0xbc,0xf0,0x23,0x01,0x00,0x00]
+ vmulsd 291(%rax,%r14,8), %xmm4, %xmm23
+
+// CHECK: vmulsd 1016(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0x7a,0x7f]
+ vmulsd 1016(%rdx), %xmm4, %xmm23
+
+// CHECK: vmulsd 1024(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0xba,0x00,0x04,0x00,0x00]
+ vmulsd 1024(%rdx), %xmm4, %xmm23
+
+// CHECK: vmulsd -1024(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0x7a,0x80]
+ vmulsd -1024(%rdx), %xmm4, %xmm23
+
+// CHECK: vmulsd -1032(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0xba,0xf8,0xfb,0xff,0xff]
+ vmulsd -1032(%rdx), %xmm4, %xmm23
// CHECK: vmulss %xmm14, %xmm10, %xmm22
// CHECK: encoding: [0x62,0xc1,0x2e,0x08,0x59,0xf6]
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