[llvm] r261490 - [X86][AVX] Add shuffle masking support for EltsFromConsecutiveLoads
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 21 11:15:48 PST 2016
Author: rksimon
Date: Sun Feb 21 13:15:48 2016
New Revision: 261490
URL: http://llvm.org/viewvc/llvm-project?rev=261490&view=rev
Log:
[X86][AVX] Add shuffle masking support for EltsFromConsecutiveLoads
Add support for the case where we have a consecutive load (which must include the first + last elements) with a mixture of undef/zero elements. We load the vector and then apply a shuffle to clear the zero'd elements.
Differential Revision: http://reviews.llvm.org/D17297
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=261490&r1=261489&r2=261490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Feb 21 13:15:48 2016
@@ -5590,7 +5590,10 @@ static SDValue EltsFromConsecutiveLoads(
EVT LDBaseVT = EltBase.getValueType();
// Consecutive loads can contain UNDEFS but not ZERO elements.
+ // Consecutive loads with UNDEFs and ZEROs elements require a
+ // an additional shuffle stage to clear the ZERO elements.
bool IsConsecutiveLoad = true;
+ bool IsConsecutiveLoadWithZeros = true;
for (int i = FirstLoadedElt + 1; i <= LastLoadedElt; ++i) {
if (LoadMask[i]) {
SDValue Elt = PeekThroughBitcast(Elts[i]);
@@ -5599,6 +5602,7 @@ static SDValue EltsFromConsecutiveLoads(
Elt.getValueType().getStoreSizeInBits() / 8,
i - FirstLoadedElt)) {
IsConsecutiveLoad = false;
+ IsConsecutiveLoadWithZeros = false;
break;
}
} else if (ZeroMask[i]) {
@@ -5628,8 +5632,9 @@ static SDValue EltsFromConsecutiveLoads(
// LOAD - all consecutive load/undefs (must start/end with a load).
// If we have found an entire vector of loads and undefs, then return a large
// load of the entire vector width starting at the base pointer.
- if (IsConsecutiveLoad && FirstLoadedElt == 0 &&
- LastLoadedElt == (int)(NumElems - 1) && ZeroMask.none()) {
+ // If the vector contains zeros, then attempt to shuffle those elements.
+ if (FirstLoadedElt == 0 && LastLoadedElt == (int)(NumElems - 1) &&
+ (IsConsecutiveLoad || IsConsecutiveLoadWithZeros)) {
assert(LDBase && "Did not find base load for merging consecutive loads");
EVT EltVT = LDBase->getValueType(0);
// Ensure that the input vector size for the merged loads matches the
@@ -5640,7 +5645,24 @@ static SDValue EltsFromConsecutiveLoads(
if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT))
return SDValue();
- return CreateLoad(VT, LDBase);
+ if (IsConsecutiveLoad)
+ return CreateLoad(VT, LDBase);
+
+ // IsConsecutiveLoadWithZeros - we need to create a shuffle of the loaded
+ // vector and a zero vector to clear out the zero elements.
+ if (!isAfterLegalize && NumElems == VT.getVectorNumElements()) {
+ SmallVector<int, 4> ClearMask(NumElems, -1);
+ for (unsigned i = 0; i < NumElems; ++i) {
+ if (ZeroMask[i])
+ ClearMask[i] = i + NumElems;
+ else if (LoadMask[i])
+ ClearMask[i] = i;
+ }
+ SDValue V = CreateLoad(VT, LDBase);
+ SDValue Z = VT.isInteger() ? DAG.getConstant(0, DL, VT)
+ : DAG.getConstantFP(0.0, DL, VT);
+ return DAG.getVectorShuffle(VT, DL, V, Z, ClearMask);
+ }
}
int LoadSize =
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll?rev=261490&r1=261489&r2=261490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll Sun Feb 21 13:15:48 2016
@@ -138,26 +138,33 @@ define <4 x float> @merge_4f32_f32_34uu(
}
define <4 x float> @merge_4f32_f32_34z6(float* %ptr) nounwind uwtable noinline ssp {
-; SSE-LABEL: merge_4f32_f32_34z6:
-; SSE: # BB#0:
-; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1,0]
-; SSE-NEXT: retq
+; SSE2-LABEL: merge_4f32_f32_34z6:
+; SSE2: # BB#0:
+; SSE2-NEXT: movups 12(%rdi), %xmm0
+; SSE2-NEXT: xorps %xmm1, %xmm1
+; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: merge_4f32_f32_34z6:
+; SSE41: # BB#0:
+; SSE41-NEXT: movups 12(%rdi), %xmm1
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3]
+; SSE41-NEXT: retq
;
; AVX-LABEL: merge_4f32_f32_34z6:
; AVX: # BB#0:
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[1,0]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vblendps {{.*#+}} xmm0 = mem[0,1],xmm0[2],mem[3]
; AVX-NEXT: retq
;
; X32-SSE-LABEL: merge_4f32_f32_34z6:
; X32-SSE: # BB#0:
; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1,0]
+; X32-SSE-NEXT: movups 12(%eax), %xmm1
+; X32-SSE-NEXT: xorps %xmm0, %xmm0
+; X32-SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3]
; X32-SSE-NEXT: retl
%ptr0 = getelementptr inbounds float, float* %ptr, i64 3
%ptr1 = getelementptr inbounds float, float* %ptr, i64 4
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll?rev=261490&r1=261489&r2=261490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll Sun Feb 21 13:15:48 2016
@@ -135,37 +135,17 @@ define <4 x double> @merge_4f64_f64_45zz
}
define <4 x double> @merge_4f64_f64_34z6(double* %ptr) nounwind uwtable noinline ssp {
-; AVX1-LABEL: merge_4f64_f64_34z6:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovups 24(%rdi), %xmm0
-; AVX1-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; AVX1-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: merge_4f64_f64_34z6:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovdqu 24(%rdi), %xmm0
-; AVX2-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; AVX2-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512F-LABEL: merge_4f64_f64_34z6:
-; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovdqu 24(%rdi), %xmm0
-; AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; AVX512F-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512F-NEXT: retq
+; AVX-LABEL: merge_4f64_f64_34z6:
+; AVX: # BB#0:
+; AVX-NEXT: vxorpd %ymm0, %ymm0, %ymm0
+; AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3]
+; AVX-NEXT: retq
;
; X32-AVX-LABEL: merge_4f64_f64_34z6:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX-NEXT: vmovups 24(%eax), %xmm0
-; X32-AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; X32-AVX-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
-; X32-AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X32-AVX-NEXT: vxorpd %ymm0, %ymm0, %ymm0
+; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3]
; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds double, double* %ptr, i64 3
%ptr1 = getelementptr inbounds double, double* %ptr, i64 4
@@ -298,11 +278,8 @@ define <8 x float> @merge_8f32_2f32_23z5
; X32-AVX-LABEL: merge_8f32_2f32_23z5:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX-NEXT: vmovupd 16(%eax), %xmm0
-; X32-AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; X32-AVX-NEXT: vxorpd %xmm2, %xmm2, %xmm2
-; X32-AVX-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm2[0],xmm1[0]
-; X32-AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X32-AVX-NEXT: vxorpd %ymm0, %ymm0, %ymm0
+; X32-AVX-NEXT: vblendpd {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3]
; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 2
%ptr1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
@@ -360,45 +337,17 @@ define <8 x float> @merge_8f32_f32_12zzu
}
define <8 x float> @merge_8f32_f32_1u3u5zu8(float* %ptr) nounwind uwtable noinline ssp {
-; AVX1-LABEL: merge_8f32_f32_1u3u5zu8:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,1],xmm0[1,0]
-; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: merge_8f32_f32_1u3u5zu8:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,1],xmm0[1,0]
-; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
-; AVX2-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX2-NEXT: retq
-;
-; AVX512F-LABEL: merge_8f32_f32_1u3u5zu8:
-; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX512F-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[1,0]
-; AVX512F-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
-; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; AVX512F-NEXT: retq
+; AVX-LABEL: merge_8f32_f32_1u3u5zu8:
+; AVX: # BB#0:
+; AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0
+; AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
+; AVX-NEXT: retq
;
; X32-AVX-LABEL: merge_8f32_f32_1u3u5zu8:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X32-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,1],xmm0[1,0]
-; X32-AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
-; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; X32-AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0
+; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds float, float* %ptr, i64 1
%ptr2 = getelementptr inbounds float, float* %ptr, i64 3
@@ -483,47 +432,27 @@ define <8 x i32> @merge_8i32_i32_56zz9uz
define <8 x i32> @merge_8i32_i32_1u3u5zu8(i32* %ptr) nounwind uwtable noinline ssp {
; AVX1-LABEL: merge_8i32_i32_1u3u5zu8:
; AVX1: # BB#0:
-; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,1,0]
-; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
-; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-NEXT: vpinsrd $2, 12(%rdi), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: merge_8i32_i32_1u3u5zu8:
; AVX2: # BB#0:
-; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,1,0]
-; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
-; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX2-NEXT: vpinsrd $2, 12(%rdi), %xmm1, %xmm1
-; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-NEXT: vpxor %ymm0, %ymm0, %ymm0
+; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; AVX2-NEXT: retq
;
; AVX512F-LABEL: merge_8i32_i32_1u3u5zu8:
; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX512F-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX512F-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,1,0]
-; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
-; AVX512F-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX512F-NEXT: vpinsrd $2, 12(%rdi), %xmm1, %xmm1
-; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX512F-NEXT: vpxor %ymm0, %ymm0, %ymm0
+; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; AVX512F-NEXT: retq
;
; X32-AVX-LABEL: merge_8i32_i32_1u3u5zu8:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,1,0]
-; X32-AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
-; X32-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-AVX-NEXT: vpinsrd $2, 12(%eax), %xmm1, %xmm1
-; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; X32-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 1
%ptr2 = getelementptr inbounds i32, i32* %ptr, i64 3
@@ -620,43 +549,27 @@ define <16 x i16> @merge_16i16_i16_0uu3u
define <16 x i16> @merge_16i16_i16_0uu3zzuuuuuzCuEF(i16* %ptr) nounwind uwtable noinline ssp {
; AVX1-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF:
; AVX1: # BB#0:
-; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vpinsrw $4, 24(%rdi), %xmm1, %xmm1
-; AVX1-NEXT: vpinsrw $6, 28(%rdi), %xmm1, %xmm1
-; AVX1-NEXT: vpinsrw $7, 30(%rdi), %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [65535,0,0,65535,0,0,0,0,0,0,0,0,65535,0,65535,65535]
+; AVX1-NEXT: vandps (%rdi), %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF:
; AVX2: # BB#0:
-; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpinsrw $4, 24(%rdi), %xmm1, %xmm1
-; AVX2-NEXT: vpinsrw $6, 28(%rdi), %xmm1, %xmm1
-; AVX2-NEXT: vpinsrw $7, 30(%rdi), %xmm1, %xmm1
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-NEXT: vmovups (%rdi), %ymm0
+; AVX2-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF:
; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX512F-NEXT: vpinsrw $4, 24(%rdi), %xmm1, %xmm1
-; AVX512F-NEXT: vpinsrw $6, 28(%rdi), %xmm1, %xmm1
-; AVX512F-NEXT: vpinsrw $7, 30(%rdi), %xmm1, %xmm1
-; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
+; AVX512F-NEXT: vmovups (%rdi), %ymm0
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; X32-AVX-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF:
; X32-AVX: # BB#0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; X32-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; X32-AVX-NEXT: vpinsrw $4, 24(%eax), %xmm1, %xmm1
-; X32-AVX-NEXT: vpinsrw $6, 28(%eax), %xmm1, %xmm1
-; X32-AVX-NEXT: vpinsrw $7, 30(%eax), %xmm1, %xmm1
-; X32-AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X32-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,0,0,65535,0,0,0,0,0,0,0,0,65535,0,65535,65535]
+; X32-AVX-NEXT: vandps (%eax), %ymm0, %ymm0
; X32-AVX-NEXT: retl
%ptr0 = getelementptr inbounds i16, i16* %ptr, i64 0
%ptr3 = getelementptr inbounds i16, i16* %ptr, i64 3
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll?rev=261490&r1=261489&r2=261490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll Sun Feb 21 13:15:48 2016
@@ -138,25 +138,19 @@ define <8 x double> @merge_8f64_f64_12zz
define <8 x double> @merge_8f64_f64_1u3u5zu8(double* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_8f64_f64_1u3u5zu8:
; ALL: # BB#0:
-; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; ALL-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
-; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; ALL-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; ALL-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
-; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; ALL-NEXT: vmovupd 8(%rdi), %zmm0
+; ALL-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; ALL-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,u,2,u,4,13,u,7>
+; ALL-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
; ALL-NEXT: retq
;
; X32-AVX512F-LABEL: merge_8f64_f64_1u3u5zu8:
; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X32-AVX512F-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
-; X32-AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
-; X32-AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; X32-AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; X32-AVX512F-NEXT: vmovupd 8(%eax), %zmm0
+; X32-AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; X32-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,0,u,u,2,0,u,u,4,0,13,0,u,u,7,0>
+; X32-AVX512F-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds double, double* %ptr, i64 1
%ptr2 = getelementptr inbounds double, double* %ptr, i64 3
@@ -231,26 +225,19 @@ define <8 x i64> @merge_8i64_i64_56zz9uz
define <8 x i64> @merge_8i64_i64_1u3u5zu8(i64* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_8i64_i64_1u3u5zu8:
; ALL: # BB#0:
-; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; ALL-NEXT: vpbroadcastq 64(%rdi), %xmm1
-; ALL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
-; ALL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; ALL-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
-; ALL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
-; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; ALL-NEXT: vmovdqu64 8(%rdi), %zmm0
+; ALL-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; ALL-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,u,2,u,4,13,u,7>
+; ALL-NEXT: vpermt2q %zmm1, %zmm2, %zmm0
; ALL-NEXT: retq
;
; X32-AVX512F-LABEL: merge_8i64_i64_1u3u5zu8:
; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT: vpinsrd $2, 64(%eax), %xmm0, %xmm0
-; X32-AVX512F-NEXT: vpinsrd $3, 68(%eax), %xmm0, %xmm0
-; X32-AVX512F-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X32-AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
-; X32-AVX512F-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X32-AVX512F-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
-; X32-AVX512F-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
-; X32-AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; X32-AVX512F-NEXT: vmovdqu32 8(%eax), %zmm0
+; X32-AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; X32-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,0,u,u,2,0,u,u,4,0,13,0,u,u,7,0>
+; X32-AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm0
; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i64, i64* %ptr, i64 1
%ptr2 = getelementptr inbounds i64, i64* %ptr, i64 3
@@ -347,27 +334,19 @@ define <16 x float> @merge_16f32_f32_0uu
define <16 x float> @merge_16f32_f32_0uu3zzuuuuuzCuEF(float* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_16f32_f32_0uu3zzuuuuuzCuEF:
; ALL: # BB#0:
-; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; ALL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; ALL-NEXT: vmovupd (%rdi), %xmm1
-; ALL-NEXT: vxorpd %xmm2, %xmm2, %xmm2
-; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; ALL-NEXT: vmovups (%rdi), %zmm0
+; ALL-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; ALL-NEXT: vmovdqa32 {{.*#+}} zmm2 = <0,u,u,3,20,21,u,u,u,u,u,u,12,29,14,15>
+; ALL-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
; ALL-NEXT: retq
;
; X32-AVX512F-LABEL: merge_16f32_f32_0uu3zzuuuuuzCuEF:
; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X32-AVX512F-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; X32-AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; X32-AVX512F-NEXT: vmovupd (%eax), %xmm1
-; X32-AVX512F-NEXT: vxorpd %xmm2, %xmm2, %xmm2
-; X32-AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; X32-AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; X32-AVX512F-NEXT: vmovups (%eax), %zmm0
+; X32-AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; X32-AVX512F-NEXT: vmovdqa32 {{.*#+}} zmm2 = <0,u,u,3,20,21,u,u,u,u,u,u,12,29,14,15>
+; X32-AVX512F-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds float, float* %ptr, i64 0
%ptr3 = getelementptr inbounds float, float* %ptr, i64 3
@@ -469,27 +448,19 @@ define <16 x i32> @merge_16i32_i32_0uu3u
define <16 x i32> @merge_16i32_i32_0uu3zzuuuuuzCuEF(i32* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_16i32_i32_0uu3zzuuuuuzCuEF:
; ALL: # BB#0:
-; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; ALL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; ALL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; ALL-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
-; ALL-NEXT: vmovdqu (%rdi), %xmm1
-; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; ALL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
-; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; ALL-NEXT: vmovdqu32 (%rdi), %zmm0
+; ALL-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; ALL-NEXT: vmovdqa32 {{.*#+}} zmm2 = <0,u,u,3,20,21,u,u,u,u,u,u,12,29,14,15>
+; ALL-NEXT: vpermt2d %zmm1, %zmm2, %zmm0
; ALL-NEXT: retq
;
; X32-AVX512F-LABEL: merge_16i32_i32_0uu3zzuuuuuzCuEF:
; X32-AVX512F: # BB#0:
; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-AVX512F-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; X32-AVX512F-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
-; X32-AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
-; X32-AVX512F-NEXT: vmovdqu (%eax), %xmm1
-; X32-AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; X32-AVX512F-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
-; X32-AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; X32-AVX512F-NEXT: vmovdqu32 (%eax), %zmm0
+; X32-AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1
+; X32-AVX512F-NEXT: vmovdqa32 {{.*#+}} zmm2 = <0,u,u,3,20,21,u,u,u,u,u,u,12,29,14,15>
+; X32-AVX512F-NEXT: vpermt2d %zmm1, %zmm2, %zmm0
; X32-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 0
%ptr3 = getelementptr inbounds i32, i32* %ptr, i64 3
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