[PATCH] D17297: [X86][AVX] Add shuffle masking support for EltsFromConsecutiveLoads

[Sanjay Patel via llvm-commits]

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.

LGTM. See inline for a couple of code comment additions.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:5589
@@ -5588,3 +5588,3 @@
 
   // Consecutive loads can contain UNDEFS but not ZERO elements.
   bool IsConsecutiveLoad = true;
----------------
Update comment to say something like: "If we have zero elts, we'll shuffle those with the vector load." ?

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:5647
@@ +5646,3 @@
+    if (!isAfterLegalize && NumElems == VT.getVectorNumElements()) {
+      SmallVector<int, 4> ClearMask(NumElems, -1);
+      for (unsigned i = 0; i < NumElems; ++i) {
----------------
Could use a comment here to explain what's going on. Something like: "Generate a mask for a shufflevector of the vector load and a zero vector."


Repository:
  rL LLVM

http://reviews.llvm.org/D17297