[llvm] r261306 - LegalizeDAG: Fix ExpandFCOPYSIGN assuming the same type on both inputs
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 18 20:44:19 PST 2016
Author: matze
Date: Thu Feb 18 22:44:19 2016
New Revision: 261306
URL: http://llvm.org/viewvc/llvm-project?rev=261306&view=rev
Log:
LegalizeDAG: Fix ExpandFCOPYSIGN assuming the same type on both inputs
Added:
llvm/trunk/test/CodeGen/AArch64/fcopysign.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=261306&r1=261305&r2=261306&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 18 22:44:19 2016
@@ -1634,6 +1634,7 @@ struct FloatSignAsInt {
MachinePointerInfo FloatPointerInfo;
SDValue IntValue;
APInt SignMask;
+ uint8_t SignBit;
};
}
@@ -1650,6 +1651,7 @@ void SelectionDAGLegalize::getSignAsIntV
if (TLI.isTypeLegal(IVT)) {
State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
State.SignMask = APInt::getSignBit(NumBits);
+ State.SignBit = NumBits - 1;
return;
}
@@ -1686,6 +1688,7 @@ void SelectionDAGLegalize::getSignAsIntV
IntPtr, State.IntPointerInfo, MVT::i8,
false, false, false, 0);
State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
+ State.SignBit = 7;
}
/// Replace the integer value produced by getSignAsIntValue() with a new value
@@ -1728,15 +1731,38 @@ SDValue SelectionDAGLegalize::ExpandFCOP
return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
}
- // Transform values to integer, copy the sign bit and transform back.
+ // Transform Mag value to integer, and clear the sign bit.
FloatSignAsInt MagAsInt;
getSignAsIntValue(MagAsInt, DL, Mag);
- assert(SignAsInt.SignMask == MagAsInt.SignMask);
- SDValue ClearSignMask = DAG.getConstant(~SignAsInt.SignMask, DL, IntVT);
- SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, MagAsInt.IntValue,
+ EVT MagVT = MagAsInt.IntValue.getValueType();
+ SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
+ SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
ClearSignMask);
- SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit);
+ // Get the signbit at the right position for MagAsInt.
+ int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
+ if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
+ if (ShiftAmount > 0) {
+ SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT);
+ SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst);
+ } else if (ShiftAmount < 0) {
+ SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT);
+ SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst);
+ }
+ SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
+ } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
+ SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
+ if (ShiftAmount > 0) {
+ SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT);
+ SignBit = DAG.getNode(ISD::SRL, DL, MagVT, SignBit, ShiftCnst);
+ } else if (ShiftAmount < 0) {
+ SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT);
+ SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst);
+ }
+ }
+
+ // Store the part with the modified sign and convert back to float.
+ SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
return modifySignAsInt(MagAsInt, DL, CopiedSign);
}
Added: llvm/trunk/test/CodeGen/AArch64/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fcopysign.ll?rev=261306&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fcopysign.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/fcopysign.ll Thu Feb 18 22:44:19 2016
@@ -0,0 +1,23 @@
+; RUN: llc -o - %s | FileCheck %s
+; Check that selection dag legalization of fcopysign works in cases with
+; different modes for the arguments.
+target triple = "aarch64--"
+
+declare fp128 @llvm.copysign.f128(fp128, fp128)
+
+ at val = global double zeroinitializer, align 8
+
+; CHECK-LABEL: copysign0
+; CHECK: ldr [[REG:x[0-9]+]], [x8, :lo12:val]
+; CHECK: and [[ANDREG:x[0-9]+]], [[REG]], #0x8000000000000000
+; CHECK: lsr x[[LSRREGNUM:[0-9]+]], [[ANDREG]], #56
+; CHECK: bfxil w[[LSRREGNUM]], w{{[0-9]+}}, #0, #7
+; CHECK: strb w[[LSRREGNUM]],
+; CHECK: ldr q{{[0-9]+}},
+define fp128 @copysign0() {
+entry:
+ %v = load double, double* @val, align 8
+ %conv = fpext double %v to fp128
+ %call = tail call fp128 @llvm.copysign.f128(fp128 0xL00000000000000007FFF000000000000, fp128 %conv) #2
+ ret fp128 %call
+}
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