[PATCH] D17341: LegalizeDAG: Use correct ptr type when expanding unaligned load/store
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 17 10:30:08 PST 2016
arsenm created this revision.
arsenm added a subscriber: llvm-commits.
This fixes regressions exposed in existing AMDGPU tests in a
future commit when all loads are custom lowered.
http://reviews.llvm.org/D17341
Files:
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -320,7 +320,6 @@
SDValue Val = ST->getValue();
EVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
- unsigned AS = ST->getAddressSpace();
SDLoc dl(ST);
if (ST->getMemoryVT().isFloatingPoint() ||
@@ -349,6 +348,7 @@
TLI.getRegisterType(*DAG.getContext(),
EVT::getIntegerVT(*DAG.getContext(),
StoredVT.getSizeInBits()));
+ EVT PtrVT = Ptr.getValueType();
unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
unsigned RegBytes = RegVT.getSizeInBits() / 8;
unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
@@ -360,8 +360,11 @@
SDValue Store = DAG.getTruncStore(Chain, dl,
Val, StackPtr, MachinePointerInfo(),
StoredVT, false, false, 0);
- SDValue Increment = DAG.getConstant(
- RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout(), AS));
+
+ EVT StackPtrVT = StackPtr.getValueType();
+
+ SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT);
+ SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT);
SmallVector<SDValue, 8> Stores;
unsigned Offset = 0;
@@ -378,9 +381,9 @@
MinAlign(ST->getAlignment(), Offset)));
// Increment the pointers.
Offset += RegBytes;
- StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
- Increment);
- Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
+ StackPtr = DAG.getNode(ISD::ADD, dl, StackPtrVT,
+ StackPtr, StackPtrIncrement);
+ Ptr = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr, PtrIncrement);
}
// The last store may be partial. Do a truncating store. On big-endian
@@ -428,9 +431,9 @@
Ptr, ST->getPointerInfo(), NewStoredVT,
ST->isVolatile(), ST->isNonTemporal(), Alignment);
- Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
- DAG.getConstant(IncrementSize, dl,
- TLI.getPointerTy(DAG.getDataLayout(), AS)));
+ EVT PtrVT = Ptr.getValueType();
+ Ptr = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
+ DAG.getConstant(IncrementSize, dl, PtrVT));
Alignment = MinAlign(Alignment, IncrementSize);
Store2 = DAG.getTruncStore(
Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
@@ -489,8 +492,7 @@
// Make sure the stack slot is also aligned for the register type.
SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
- SDValue Increment =
- DAG.getConstant(RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout()));
+ SDValue Increment = DAG.getConstant(RegBytes, dl, Ptr.getValueType());
SmallVector<SDValue, 8> Stores;
SDValue StackPtr = StackBase;
unsigned Offset = 0;
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