[PATCH] D17098: [AArch64] analyse dependences of ldp/stp

[Chad Rosier via llvm-commits]

mcrosier requested changes to this revision.
mcrosier added a reviewer: mcrosier.
mcrosier added a comment.
This revision now requires changes to proceed.

All of the provided tests pass on current top of trunk (i.e., without this patch).  We'll need some tests that exercise the patch before it can be committed.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:1346
@@ +1345,3 @@
+  // Handle only loads/stores with base register followed by immediate offset
+  // or pairs.
+  if (LdSt->getNumOperands() == 3) {
----------------
I think the 'or' is misleading as we're looking for a base register followed by an immediate offset in both the non-paired and paired cases.

We're looking for   'ldr x1, [x0, #imm]'  or  'ldp x1, x2, [x0, #imm]'

Therefore, I'd suggest leaving this comment as is and add comments below.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:1348
@@ +1347,3 @@
+  if (LdSt->getNumOperands() == 3) {
+    if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
+        return false;
----------------
// Non-paired instruction (e.g., ldr x1, [x0, #8]).

================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:1351
@@ +1350,3 @@
+  } else if (LdSt->getNumOperands() == 4) {
+    if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isReg() || !LdSt->getOperand(3).isImm())
+      return false;
----------------
// Paired instruction (e.g., ldp x1, x2, [x0, #8]).


http://reviews.llvm.org/D17098