[PATCH] D16723: [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target.

[Tom Stellard via llvm-commits]

tstellarAMD requested changes to this revision.
tstellarAMD added a comment.
This revision now requires changes to proceed.

The encoding of the dmask field is incorrect with this patch.  You may want to split the dmask changes into a separate patch. Here is an example test case:

Good Encoding: image_sample v[0:2], 13, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800D00 00030002
Bad Encoding:   image_sample v[0:2], 13, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[0:3] ; F0800700 00030002

target triple = "amdgcn--"

define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, i32 addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, float) #0 {
main_body:

  %22 = getelementptr [17 x <8 x i32>], [17 x <8 x i32>] addrspace(2)* %2, i64 0, i64 0
  %23 = load <8 x i32>, <8 x i32> addrspace(2)* %22, align 32, !tbaa !0
  %24 = bitcast [17 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
  %25 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %24, i64 0, i64 3
  %26 = load <4 x i32>, <4 x i32> addrspace(2)* %25, align 16, !tbaa !0
  %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
  %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
  %29 = bitcast float %27 to i32
  %30 = bitcast float %28 to i32
  %31 = insertelement <2 x i32> undef, i32 %29, i32 0
  %32 = insertelement <2 x i32> %31, i32 %30, i32 1
  %33 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %32, <8 x i32> %23, <4 x i32> %26, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  %34 = extractelement <4 x float> %33, i32 0
  %35 = extractelement <4 x float> %33, i32 2
  %36 = extractelement <4 x float> %33, i32 3
  %37 = call i32 @llvm.SI.packf16(float %34, float 0.000000e+00)
  %38 = bitcast i32 %37 to float
  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
  %40 = bitcast i32 %39 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float undef, float undef)
  ret void

}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = !{!"const", null, i32 1}


http://reviews.llvm.org/D16723