[llvm] r260774 - AMDGPU/SI: Add instruction defs for VOP1 DPP instructions
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 12 16:51:31 PST 2016
Author: tstellar
Date: Fri Feb 12 18:51:31 2016
New Revision: 260774
URL: http://llvm.org/viewvc/llvm-project?rev=260774&view=rev
Log:
AMDGPU/SI: Add instruction defs for VOP1 DPP instructions
Reviewers: nhaustov, cfang, arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D17159
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=260774&r1=260773&r2=260774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Fri Feb 12 18:51:31 2016
@@ -1083,6 +1083,11 @@ class getVOPSrc1ForVT<ValueType VT> {
RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
}
+// Returns the register class to use for DPP source operands.
+class getDPPSrcForVT<ValueType VT> {
+ RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
+}
+
// Returns the register class to use for sources of VOP3 instructions for the
// given VT.
class getVOP3SrcForVT<ValueType VT> {
@@ -1150,6 +1155,34 @@ class getIns64 <RegisterOperand Src0RC,
/* endif */ )));
}
+class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
+ bit HasModifiers> {
+
+ dag ret = !if (!eq(NumSrcArgs, 1),
+ !if (!eq(HasModifiers, 1),
+ // VOP1_DPP with modifiers
+ (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
+ i32imm:$dpp_ctrl, i1imm:$bound_ctrl,
+ i32imm:$bank_mask, i32imm:$row_mask)
+ /* else */,
+ // VOP1_DPP without modifiers
+ (ins Src0RC:$src0, i32imm:$dpp_ctrl, i1imm:$bound_ctrl,
+ i32imm:$bank_mask, i32imm:$row_mask)
+ /* endif */)
+ /* NumSrcArgs == 2 */,
+ !if (!eq(HasModifiers, 1),
+ // VOP2_DPP with modifiers
+ (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
+ InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
+ i32imm:$dpp_ctrl, i1imm:$bound_ctrl,
+ i32imm:$bank_mask, i32imm:$row_mask)
+ /* else */,
+ // VOP2_DPP without modifiers
+ (ins Src0RC:$src0, Src1RC:$src1, i32imm:$dpp_ctrl, i1imm:$bound_ctrl,
+ i32imm:$bank_mask, i32imm:$row_mask)
+ /* endif */));
+}
+
// Returns the assembly string for the inputs and outputs of a VOP[12C]
// instruction. This does not add the _e32 suffix, so it can be reused
// by getAsm64.
@@ -1178,6 +1211,17 @@ class getAsm64 <bit HasDst, int NumSrcAr
"$dst, "#src0#src1#src2#"$clamp"#"$omod");
}
+class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers> {
+ string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
+ string src1 = !if(!eq(NumSrcArgs, 1), "",
+ !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
+ " $src1_modifiers,"));
+ string args = !if(!eq(HasModifiers, 0),
+ getAsm32<0, NumSrcArgs>.ret,
+ src0#src1);
+ string ret = " $dst"#args#", $dpp_ctrl, "#"$bound_ctrl, "#"$bank_mask, "#"$row_mask";
+}
+
class VOPProfile <list<ValueType> _ArgVT> {
field list<ValueType> ArgVT = _ArgVT;
@@ -1187,11 +1231,14 @@ class VOPProfile <list<ValueType> _ArgVT
field ValueType Src1VT = ArgVT[2];
field ValueType Src2VT = ArgVT[3];
field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
+ field RegisterClass DstRCDPP = !if(!eq(DstVT.Size, 64), VReg_64, VGPR_32);
field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
+ field RegisterClass Src0DPP = getDPPSrcForVT<Src0VT>.ret;
+ field RegisterClass Src1DPP = getDPPSrcForVT<Src1VT>.ret;
field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
field bit HasDst32 = HasDst;
@@ -1204,13 +1251,16 @@ class VOPProfile <list<ValueType> _ArgVT
// output. This is manually overridden for them.
field dag Outs32 = Outs;
field dag Outs64 = Outs;
+ field dag OutsDPP = (outs DstRCDPP:$dst);
field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
HasModifiers>.ret;
+ field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs, HasModifiers>.ret;
field string Asm32 = getAsm32<HasDst, NumSrcArgs>.ret;
field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers>.ret;
+ field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers>.ret;
}
// FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
@@ -1428,6 +1478,16 @@ multiclass VOP1_m <vop1 op, string opNam
}
+class VOP1_DPP <vop1 op, string opName, VOPProfile p> :
+ VOP1_DPPe <op.VI>,
+ VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, []> {
+ // FIXME: remove when we are using the correct names for the encoding fields.
+ field bit vdst = 0;
+ let AssemblerPredicates = [isVI];
+ let src0_modifiers = !if(p.HasModifiers, ?, 0);
+ let src1_modifiers = 0;
+}
+
multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
string asm = opName#p.Asm32> {
@@ -1675,6 +1735,8 @@ multiclass VOP1_Helper <vop1 op, string
defm _e64 : VOP3_1_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
p.HasModifiers>;
+
+ def _dpp : VOP1_DPP <op, opName, p>;
}
multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
Modified: llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td?rev=260774&r1=260773&r2=260774&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td Fri Feb 12 18:51:31 2016
@@ -157,6 +157,51 @@ class VOP3be_vi <bits<10> op> : Enc64 {
let Inst{63} = src2_modifiers{0};
}
+class VOP_DPP <dag outs, dag ins, string asm, list<dag> pattern> :
+ VOPAnyCommon <outs, ins, asm, pattern> {
+ let Size = 8;
+}
+
+class VOP_DPPe : Enc64 {
+ bits<2> src0_modifiers;
+ bits<8> src0;
+ bits<2> src1_modifiers;
+ bits<9> dpp_ctrl;
+ bits<1> bound_ctrl;
+ bits<4> bank_mask;
+ bits<4> row_mask;
+
+ let Inst{39-32} = src0;
+ let Inst{48-40} = dpp_ctrl;
+ let Inst{51} = bound_ctrl;
+ let Inst{52} = src0_modifiers{0}; // src0_neg
+ let Inst{53} = src0_modifiers{1}; // src0_abs
+ let Inst{54} = src1_modifiers{0}; // src1_neg
+ let Inst{55} = src1_modifiers{1}; // src1_abs
+ let Inst{59-56} = bank_mask;
+ let Inst{63-60} = row_mask;
+}
+
+class VOP1_DPPe <bits<8> op> : VOP_DPPe {
+ bits<8> dst;
+
+ let Inst{8-0} = 0xfa; // dpp
+ let Inst{16-9} = op;
+ let Inst{24-17} = dst;
+ let Inst{31-25} = 0x3f; //encoding
+}
+
+class VOP2_DPPe <bits<6> op> : Enc32 {
+ bits<8> dst;
+ bits<8> src1;
+
+ let Inst{8-0} = 0xfa; //dpp
+ let Inst{16-9} = src1;
+ let Inst{24-17} = dst;
+ let Inst{30-25} = op;
+ let Inst{31} = 0x0; //encoding
+}
+
class EXPe_vi : EXPe {
let Inst{31-26} = 0x31; //encoding
}
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