[llvm] r260588 - AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklist

Tom Stellard via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 11 13:14:34 PST 2016


Author: tstellar
Date: Thu Feb 11 15:14:34 2016
New Revision: 260588

URL: http://llvm.org/viewvc/llvm-project?rev=260588&view=rev
Log:
AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklist

Summary:
When we split SMRD instructions into two MUBUFs we were adding the users
of the newly created MUBUFs to the VALU worklist.  However, the only
users these instructions had was the REG_SEQUENCE that was inserted
by splitSMRD when the original SMRD instruction was split.

We need to make sure to add the users of the original SMRD to the VALU
worklist before it is split.

I have a test case, but it requires one other bug fix, so it will be
added in a later commt.

Reviewers: mareko, arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D17101

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=260588&r1=260587&r2=260588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Feb 11 15:14:34 2016
@@ -2411,6 +2411,7 @@ void SIInstrInfo::moveSMRDToVALU(Machine
     }
     case 32: {
       MachineInstr *Lo, *Hi;
+      addUsersToMoveToVALUWorklist(MI->getOperand(0).getReg(), MRI, Worklist);
       splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
                 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
       MI->eraseFromParent();
@@ -2421,6 +2422,7 @@ void SIInstrInfo::moveSMRDToVALU(Machine
 
     case 64: {
       MachineInstr *Lo, *Hi;
+      addUsersToMoveToVALUWorklist(MI->getOperand(0).getReg(), MRI, Worklist);
       splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
                 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
       MI->eraseFromParent();




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