[PATCH] D15703: [AVR] Add instruction definitions

[Matt Arsenault via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

LGTM.

The tablegen formatting looks weird to me, but there don't seem to be any consistently followed standards there.


================
Comment at: lib/Target/AVR/AVRInstrInfo.td:64
@@ +63,3 @@
+
+// pseudo shift nodes for non-constant shift amounts
+def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
----------------
Should be capitalized  and end with a period

================
Comment at: lib/Target/AVR/AVRInstrInfo.td:649
@@ +648,3 @@
+                    "ori\t$rd, $k",
+                    [(set LD8:$rd, (or LD8:$src, imm:$k)),
+                     (implicit SREG)]>;
----------------
You should just be able to  use i8:$src instead of the specific register class in these patterns


http://reviews.llvm.org/D15703