[PATCH] D17000: [AArch64] Reduce number of callee-save save/restores.

[Geoff Berry via llvm-commits]

gberry created this revision.
gberry added reviewers: t.p.northover, rengolin, mcrosier, jmolloy.
gberry added a subscriber: llvm-commits.
Herald added subscribers: mcrosier, rengolin, aemerson.

Before this change, callee-save registers would be rounded up to even
pairs of GPRs and FPRs.  This change eliminates these extra padding
load/stores, though it does keep the stack allocation the same size
unless both the GPR and FPR sets have an odd size, in which case one
full pair stack slot (16 bytes) is saved.

http://reviews.llvm.org/D17000

Files:
  lib/Target/AArch64/AArch64FrameLowering.cpp
  test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
  test/CodeGen/AArch64/alloca.ll
  test/CodeGen/AArch64/arm64-frame-index.ll
  test/CodeGen/AArch64/arm64-inline-asm.ll
  test/CodeGen/AArch64/arm64-register-pairing.ll
  test/CodeGen/AArch64/arm64-shrink-wrapping.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D17000.47248.patch
Type: text/x-patch
Size: 23226 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160208/ca5c9a22/attachment.bin>