[PATCH] D16863: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL259897: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors (authored by tstellar).

Changed prior to commit:
  http://reviews.llvm.org/D16863?vs=46962&id=47028#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D16863

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h

Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -37,8 +37,8 @@
   AMDGPUIntrinsicInfo IntrinsicInfo;
 
 public:
-  AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef FS,
-                      StringRef CPU, TargetOptions Options, Reloc::Model RM,
+  AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+                      StringRef FS, TargetOptions Options, Reloc::Model RM,
                       CodeModel::Model CM, CodeGenOpt::Level OL);
   ~AMDGPUTargetMachine();
 
@@ -63,8 +63,8 @@
 class R600TargetMachine : public AMDGPUTargetMachine {
 
 public:
-  R600TargetMachine(const Target &T, const Triple &TT, StringRef FS,
-                    StringRef CPU, TargetOptions Options, Reloc::Model RM,
+  R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+                    StringRef FS, TargetOptions Options, Reloc::Model RM,
                     CodeModel::Model CM, CodeGenOpt::Level OL);
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
@@ -77,8 +77,8 @@
 class GCNTargetMachine : public AMDGPUTargetMachine {
 
 public:
-  GCNTargetMachine(const Target &T, const Triple &TT, StringRef FS,
-                   StringRef CPU, TargetOptions Options, Reloc::Model RM,
+  GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+                   StringRef FS, TargetOptions Options, Reloc::Model RM,
                    CodeModel::Model CM, CodeGenOpt::Level OL);
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -124,20 +124,20 @@
 //===----------------------------------------------------------------------===//
 
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
-                                     StringRef FS, StringRef CPU,
+                                     StringRef CPU, StringRef FS,
                                      TargetOptions Options, Reloc::Model RM,
                                      CodeModel::Model CM, CodeGenOpt::Level OL)
-    : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
+    : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
 
 //===----------------------------------------------------------------------===//
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
-                                   StringRef FS, StringRef CPU,
+                                   StringRef CPU, StringRef FS,
                                    TargetOptions Options, Reloc::Model RM,
                                    CodeModel::Model CM, CodeGenOpt::Level OL)
-    : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
+    : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
 
 //===----------------------------------------------------------------------===//
 // AMDGPU Pass Setup


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