[PATCH] D16920: [AMDGPU] Rename $dst operand to $vdst for VOP instructions.

[Matt Arsenault via llvm-commits]

arsenm added inline comments.

================
Comment at: lib/Target/AMDGPU/SIInstrInfo.td:1830
@@ -1825,3 +1829,3 @@
 
-  defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
+  defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$vdst), p.Ins64, opName#p.Asm64, pat64,
                         opName, p.HasModifiers, DefExec, revOp, sched>;
----------------
SamWot wrote:
> arsenm wrote:
> > This is a scalar output, so it should not be a vdst
> Here is problem with output operand name. Purpose of this renaming is to match operands names and names of fields in instruction encoding. VOPC instructions with 64-bit encoding use instruction format VOP3e:
> 
> ```
> class VOP3e <bits<9> op> : Enc64 {
>   bits<8> vdst;
>   bits<2> src0_modifiers;
>   bits<9> src0;
>   bits<2> src1_modifiers;
>   bits<9> src1;
>   bits<2> src2_modifiers;
>   bits<9> src2;
>   bits<1> clamp;
>   bits<2> omod;
> 
>   let Inst{7-0} = vdst;
>   let Inst{8} = src0_modifiers{1};
>   let Inst{9} = src1_modifiers{1};
>   let Inst{10} = src2_modifiers{1};
>   let Inst{11} = clamp;
>   let Inst{25-17} = op;
>   let Inst{31-26} = 0x34; //encoding
>   let Inst{40-32} = src0;
>   let Inst{49-41} = src1;
>   let Inst{58-50} = src2;
>   let Inst{60-59} = omod;
>   let Inst{61} = src0_modifiers{0};
>   let Inst{62} = src1_modifiers{0};
>   let Inst{63} = src2_modifiers{0};
> }
> ```
> This encoding correspond to VOP3a encoding from spec. It does not have fields for output operands other than vdst. Thats why I renamed operand to $vdst.
> 
> Possibly we should change VOPC instructions format to VOP3be as it is stated in spec.
> 
> 
> 
> 
> 
> 
> 
Yes, this should be fixed. I'm surprised it doesn't matter


http://reviews.llvm.org/D16920