[PATCH] D16581: llvm-mc. Enables eip-relative addressing.
Derek Schuff via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 09:24:17 PST 2016
This revision was automatically updated to reflect the committed changes.
Closed by commit rL259528: [MC] Enable eip-relative addressing on x86-64 for X32 ABI (authored by dschuff).
Changed prior to commit:
http://reviews.llvm.org/D16581?vs=46118&id=46664#toc
Repository:
rL LLVM
http://reviews.llvm.org/D16581
Files:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/test/MC/X86/x86-64.s
Index: llvm/trunk/test/MC/X86/x86-64.s
===================================================================
--- llvm/trunk/test/MC/X86/x86-64.s
+++ llvm/trunk/test/MC/X86/x86-64.s
@@ -592,6 +592,31 @@
// CHECK: encoding: [0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
// CHECK: fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte
+movl foo(%eip), %eax
+// CHECK: movl foo(%eip), %eax
+// CHECK: encoding: [0x67,0x8b,0x05,A,A,A,A]
+// CHECK: fixup A - offset: 3, value: foo-4, kind: reloc_riprel_4byte
+
+movb $12, foo(%eip)
+// CHECK: movb $12, foo(%eip)
+// CHECK: encoding: [0x67,0xc6,0x05,A,A,A,A,0x0c]
+// CHECK: fixup A - offset: 3, value: foo-5, kind: reloc_riprel_4byte
+
+movw $12, foo(%eip)
+// CHECK: movw $12, foo(%eip)
+// CHECK: encoding: [0x67,0x66,0xc7,0x05,A,A,A,A,0x0c,0x00]
+// CHECK: fixup A - offset: 4, value: foo-6, kind: reloc_riprel_4byte
+
+movl $12, foo(%eip)
+// CHECK: movl $12, foo(%eip)
+// CHECK: encoding: [0x67,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
+// CHECK: fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte
+
+movq $12, foo(%eip)
+// CHECK: movq $12, foo(%eip)
+// CHECK: encoding: [0x67,0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00]
+// CHECK: fixup A - offset: 4, value: foo-8, kind: reloc_riprel_4byte
+
// CHECK: addq $-424, %rax
// CHECK: encoding: [0x48,0x05,0x58,0xfe,0xff,0xff]
addq $-424, %rax
@@ -607,6 +632,15 @@
// CHECK: fixup A - offset: 3, value: _foo at GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
movq _foo at GOTPCREL(%rip), %r14
+// CHECK: movq _foo at GOTPCREL(%eip), %rax
+// CHECK: encoding: [0x67,0x48,0x8b,0x05,A,A,A,A]
+// CHECK: fixup A - offset: 4, value: _foo at GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
+movq _foo at GOTPCREL(%eip), %rax
+
+// CHECK: movq _foo at GOTPCREL(%eip), %r14
+// CHECK: encoding: [0x67,0x4c,0x8b,0x35,A,A,A,A]
+// CHECK: fixup A - offset: 4, value: _foo at GOTPCREL-4, kind: reloc_riprel_4byte_movq_load
+movq _foo at GOTPCREL(%eip), %r14
// CHECK: movq (%r13,%rax,8), %r13
// CHECK: encoding: [0x4d,0x8b,0x6c,0xc5,0x00]
Index: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -231,6 +231,10 @@
(IndexReg.getReg() != 0 &&
X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
return true;
+ if (BaseReg.getReg() == X86::EIP) {
+ assert(IndexReg.getReg() == 0 && "Invalid eip-based address.");
+ return true;
+ }
return false;
}
@@ -373,7 +377,8 @@
bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
// Handle %rip relative addressing.
- if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
+ if (BaseReg == X86::RIP ||
+ BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
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