[PATCH] D16807: [mips] MUL macro variations

[Srdjan Obucina via llvm-commits]

obucina added a comment.

In original test example there is one more instruction

dmul $4, $5, $6

However, there is a DMUL instruction in TD files, available only for Cavium Octeon, with predicate [HasCnMips], so I am getting "error: instruction requires a CPU feature not currently enabled" when I try to process this instruction.

I need advice on how to handle this situation. One solution is to define new DMUL pseudo instruction for everything but CnMips. Existing DMUL appears as a processor specific instruction, and not a general one, so I am wondering about naming conventions, should I leave existing DMUL as is, or rename it to reflect its nature.


http://reviews.llvm.org/D16807