[PATCH] D16220: [mips] Fix RetCC_MipsN to promote types smaller than i64 to GPR-width.

[Vasileios Kalintiris via llvm-commits]

vkalintiris updated this revision to Diff 46642.
vkalintiris marked 23 inline comments as done.
vkalintiris added a comment.

Addressed Daniel's comments.

As far as I can tell, almost all of our redundant sign-extensions come from the
usage of the 32-bit version of our instructions.


http://reviews.llvm.org/D16220

Files:
  lib/Target/Mips/MipsCallingConv.td
  lib/Target/Mips/MipsISelLowering.cpp
  test/CodeGen/Mips/atomic.ll
  test/CodeGen/Mips/cconv/return.ll
  test/CodeGen/Mips/delay-slot-kill.ll
  test/CodeGen/Mips/fcmp.ll
  test/CodeGen/Mips/llvm-ir/add.ll
  test/CodeGen/Mips/llvm-ir/and.ll
  test/CodeGen/Mips/llvm-ir/ashr.ll
  test/CodeGen/Mips/llvm-ir/lshr.ll
  test/CodeGen/Mips/llvm-ir/mul.ll
  test/CodeGen/Mips/llvm-ir/or.ll
  test/CodeGen/Mips/llvm-ir/ret.ll
  test/CodeGen/Mips/llvm-ir/sdiv.ll
  test/CodeGen/Mips/llvm-ir/select-dbl.ll
  test/CodeGen/Mips/llvm-ir/select-flt.ll
  test/CodeGen/Mips/llvm-ir/select-int.ll
  test/CodeGen/Mips/llvm-ir/shl.ll
  test/CodeGen/Mips/llvm-ir/srem.ll
  test/CodeGen/Mips/llvm-ir/sub.ll
  test/CodeGen/Mips/llvm-ir/udiv.ll
  test/CodeGen/Mips/llvm-ir/urem.ll
  test/CodeGen/Mips/llvm-ir/xor.ll
  test/CodeGen/Mips/msa/basic_operations.ll
  test/CodeGen/Mips/named-register-n32.ll

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