[PATCH] D16803: Use ComputeNumSignBits to fold (sext_inreg (trunc x)) -> (trunc x)

[Vasileios Kalintiris via llvm-commits]

vkalintiris created this revision.
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: llvm-commits.

If x's number of sign bits is greater than the number of sign bits
introduced by the sext_inreg, then we can skip the sign extension.

I can't think of any way to test this. I tried to using csmith without any
luck. This patch is intended for D16220.

http://reviews.llvm.org/D16803

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6915,6 +6915,16 @@
       return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
   }
 
+  // fold (sext_in_reg (trunc x)) -> (trunc x) if x's sign bits start from
+  // EVTBits.
+  if (N0.getOpcode() == ISD::TRUNCATE) {
+    unsigned N00VTBits = N0.getOperand(0).getValueType().getSizeInBits();
+    unsigned N00NSB = DAG.ComputeNumSignBits(N0.getOperand(0));
+
+    if ((N00VTBits - N00NSB + 1) <= EVTBits)
+      return N0;
+  }
+
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
   if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
     return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);


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