[PATCH] D16785: [AArch64] AArch64LoadStoreOptimizer: fix bug in pre-inc check iterator
Geoff Berry via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 1 13:32:35 PST 2016
gberry updated this revision to Diff 46576.
gberry added a comment.
Address Chad's comments.
http://reviews.llvm.org/D16785
Files:
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
test/CodeGen/AArch64/arm64-nvcast.ll
Index: test/CodeGen/AArch64/arm64-nvcast.ll
===================================================================
--- test/CodeGen/AArch64/arm64-nvcast.ll
+++ test/CodeGen/AArch64/arm64-nvcast.ll
@@ -2,7 +2,7 @@
; CHECK-LABEL: _test:
; CHECK: fmov.2d v0, #2.00000000
-; CHECK: str q0, [sp]
+; CHECK: str q0, [sp, #-16]!
; CHECK: mov x8, sp
; CHECK: ldr s0, [x8, w1, sxtw #2]
; CHECK: str s0, [x0]
@@ -16,7 +16,7 @@
; CHECK-LABEL: _test2
; CHECK: movi.16b v0, #0x3f
-; CHECK: str q0, [sp]
+; CHECK: str q0, [sp, #-16]!
; CHECK: mov x8, sp
; CHECK: ldr s0, [x8, w1, sxtw #2]
; CHECK: str s0, [x0]
Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
===================================================================
--- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -954,6 +954,8 @@
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
if (MO.isDef()) {
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
ModifiedRegs.set(*AI);
@@ -1431,12 +1433,9 @@
BitVector ModifiedRegs, UsedRegs;
ModifiedRegs.resize(TRI->getNumRegs());
UsedRegs.resize(TRI->getNumRegs());
- --MBBI;
- for (; MBBI != B; --MBBI) {
+ do {
+ --MBBI;
MachineInstr *MI = MBBI;
- // Skip DBG_VALUE instructions.
- if (MI->isDebugValue())
- continue;
// If we found a match, return it.
if (isMatchingUpdateInsn(I, MI, BaseReg, Offset))
@@ -1449,7 +1448,7 @@
// return early.
if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
return E;
- }
+ } while (MBBI != B);
return E;
}
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