[llvm] r259405 - Regenerate vector sext/zext constant folding tests.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 1 13:01:29 PST 2016
Author: rksimon
Date: Mon Feb 1 15:01:29 2016
New Revision: 259405
URL: http://llvm.org/viewvc/llvm-project?rev=259405&view=rev
Log:
Regenerate vector sext/zext constant folding tests.
Modified:
llvm/trunk/test/CodeGen/X86/fold-vector-sext-zext.ll
Modified: llvm/trunk/test/CodeGen/X86/fold-vector-sext-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-vector-sext-zext.ll?rev=259405&r1=259404&r2=259405&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-vector-sext-zext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-vector-sext-zext.ll Mon Feb 1 15:01:29 2016
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; Verify that the backend correctly folds a sign/zero extend of a vector where
@@ -6,8 +7,11 @@
; simple loads from constant pool of the result. That is because the resulting
; vector should be known at static time.
-
define <4 x i16> @test1() {
+; CHECK-LABEL: test1:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,4294967295,2,4294967293]
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 0, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -15,11 +19,12 @@ define <4 x i16> @test1() {
%5 = sext <4 x i8> %4 to <4 x i16>
ret <4 x i16> %5
}
-; CHECK-LABEL: test1
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i16> @test2() {
+; CHECK-LABEL: test2:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,4294967295,u,4294967293>
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 undef, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 undef, i32 2
@@ -27,11 +32,12 @@ define <4 x i16> @test2() {
%5 = sext <4 x i8> %4 to <4 x i16>
ret <4 x i16> %5
}
-; CHECK-LABEL: test2
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i32> @test3() {
+; CHECK-LABEL: test3:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,4294967295,2,4294967293]
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 0, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -39,11 +45,12 @@ define <4 x i32> @test3() {
%5 = sext <4 x i8> %4 to <4 x i32>
ret <4 x i32> %5
}
-; CHECK-LABEL: test3
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i32> @test4() {
+; CHECK-LABEL: test4:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,4294967295,u,4294967293>
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 undef, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 undef, i32 2
@@ -51,12 +58,12 @@ define <4 x i32> @test4() {
%5 = sext <4 x i8> %4 to <4 x i32>
ret <4 x i32> %5
}
-; CHECK-LABEL: test4
-; CHECK: vmovaps
-; CHECK-NEXT: ret
-
define <4 x i64> @test5() {
+; CHECK-LABEL: test5:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,18446744073709551615,2,18446744073709551613]
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 0, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -64,12 +71,12 @@ define <4 x i64> @test5() {
%5 = sext <4 x i8> %4 to <4 x i64>
ret <4 x i64> %5
}
-; CHECK-LABEL: test5
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i64> @test6() {
+; CHECK-LABEL: test6:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <u,18446744073709551615,u,18446744073709551613>
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 undef, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 undef, i32 2
@@ -77,12 +84,12 @@ define <4 x i64> @test6() {
%5 = sext <4 x i8> %4 to <4 x i64>
ret <4 x i64> %5
}
-; CHECK-LABEL: test6
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i16> @test7() {
+; CHECK-LABEL: test7:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <0,65535,2,65533,u,u,u,u>
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 0, i32 0
%2 = insertelement <8 x i8> %1, i8 -1, i32 1
%3 = insertelement <8 x i8> %2, i8 2, i32 2
@@ -94,11 +101,12 @@ define <8 x i16> @test7() {
%9 = sext <8 x i8> %4 to <8 x i16>
ret <8 x i16> %9
}
-; CHECK-LABEL: test7
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i32> @test8() {
+; CHECK-LABEL: test8:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <0,4294967295,2,4294967293,u,u,u,u>
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 0, i32 0
%2 = insertelement <8 x i8> %1, i8 -1, i32 1
%3 = insertelement <8 x i8> %2, i8 2, i32 2
@@ -110,12 +118,12 @@ define <8 x i32> @test8() {
%9 = sext <8 x i8> %4 to <8 x i32>
ret <8 x i32> %9
}
-; CHECK-LABEL: test8
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i16> @test9() {
+; CHECK-LABEL: test9:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,65535,u,65533,u,u,u,u>
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 undef, i32 0
%2 = insertelement <8 x i8> %1, i8 -1, i32 1
%3 = insertelement <8 x i8> %2, i8 undef, i32 2
@@ -127,11 +135,12 @@ define <8 x i16> @test9() {
%9 = sext <8 x i8> %4 to <8 x i16>
ret <8 x i16> %9
}
-; CHECK-LABEL: test9
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i32> @test10() {
+; CHECK-LABEL: test10:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <0,u,2,u,u,u,u,u>
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 0, i32 0
%2 = insertelement <8 x i8> %1, i8 undef, i32 1
%3 = insertelement <8 x i8> %2, i8 2, i32 2
@@ -143,13 +152,12 @@ define <8 x i32> @test10() {
%9 = sext <8 x i8> %4 to <8 x i32>
ret <8 x i32> %9
}
-; CHECK-LABEL: test10
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
-
define <4 x i16> @test11() {
+; CHECK-LABEL: test11:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,2,253]
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 0, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -157,11 +165,12 @@ define <4 x i16> @test11() {
%5 = zext <4 x i8> %4 to <4 x i16>
ret <4 x i16> %5
}
-; CHECK-LABEL: test11
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i32> @test12() {
+; CHECK-LABEL: test12:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,2,253]
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 0, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -169,11 +178,12 @@ define <4 x i32> @test12() {
%5 = zext <4 x i8> %4 to <4 x i32>
ret <4 x i32> %5
}
-; CHECK-LABEL: test12
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i64> @test13() {
+; CHECK-LABEL: test13:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,2,253]
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 0, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -181,12 +191,12 @@ define <4 x i64> @test13() {
%5 = zext <4 x i8> %4 to <4 x i64>
ret <4 x i64> %5
}
-; CHECK-LABEL: test13
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i16> @test14() {
+; CHECK-LABEL: test14:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253>
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 undef, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 undef, i32 2
@@ -194,11 +204,12 @@ define <4 x i16> @test14() {
%5 = zext <4 x i8> %4 to <4 x i16>
ret <4 x i16> %5
}
-; CHECK-LABEL: test14
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i32> @test15() {
+; CHECK-LABEL: test15:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <0,u,2,u>
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 0, i32 0
%2 = insertelement <4 x i8> %1, i8 undef, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -206,11 +217,12 @@ define <4 x i32> @test15() {
%5 = zext <4 x i8> %4 to <4 x i32>
ret <4 x i32> %5
}
-; CHECK-LABEL: test15
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <4 x i64> @test16() {
+; CHECK-LABEL: test16:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <u,255,2,u>
+; CHECK-NEXT: retq
%1 = insertelement <4 x i8> undef, i8 undef, i32 0
%2 = insertelement <4 x i8> %1, i8 -1, i32 1
%3 = insertelement <4 x i8> %2, i8 2, i32 2
@@ -218,12 +230,12 @@ define <4 x i64> @test16() {
%5 = zext <4 x i8> %4 to <4 x i64>
ret <4 x i64> %5
}
-; CHECK-LABEL: test16
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i16> @test17() {
+; CHECK-LABEL: test17:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,2,253,4,251,6,249]
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 0, i32 0
%2 = insertelement <8 x i8> %1, i8 -1, i32 1
%3 = insertelement <8 x i8> %2, i8 2, i32 2
@@ -235,11 +247,12 @@ define <8 x i16> @test17() {
%9 = zext <8 x i8> %8 to <8 x i16>
ret <8 x i16> %9
}
-; CHECK-LABEL: test17
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i32> @test18() {
+; CHECK-LABEL: test18:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,2,253,4,251,6,249]
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 0, i32 0
%2 = insertelement <8 x i8> %1, i8 -1, i32 1
%3 = insertelement <8 x i8> %2, i8 2, i32 2
@@ -251,12 +264,12 @@ define <8 x i32> @test18() {
%9 = zext <8 x i8> %8 to <8 x i32>
ret <8 x i32> %9
}
-; CHECK-LABEL: test18
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i16> @test19() {
+; CHECK-LABEL: test19:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = <u,255,u,253,u,251,u,249>
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 undef, i32 0
%2 = insertelement <8 x i8> %1, i8 -1, i32 1
%3 = insertelement <8 x i8> %2, i8 undef, i32 2
@@ -268,11 +281,12 @@ define <8 x i16> @test19() {
%9 = zext <8 x i8> %8 to <8 x i16>
ret <8 x i16> %9
}
-; CHECK-LABEL: test19
-; CHECK: vmovaps
-; CHECK-NEXT: ret
define <8 x i32> @test20() {
+; CHECK-LABEL: test20:
+; CHECK: # BB#0:
+; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <0,u,2,253,4,u,6,u>
+; CHECK-NEXT: retq
%1 = insertelement <8 x i8> undef, i8 0, i32 0
%2 = insertelement <8 x i8> %1, i8 undef, i32 1
%3 = insertelement <8 x i8> %2, i8 2, i32 2
@@ -284,8 +298,3 @@ define <8 x i32> @test20() {
%9 = zext <8 x i8> %8 to <8 x i32>
ret <8 x i32> %9
}
-; CHECK-LABEL: test20
-; CHECK-NOT: vinsertf128
-; CHECK: vmovaps
-; CHECK-NEXT: ret
-
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