[PATCH] D15302: [Greedy regalloc] Replace analyzeSiblingValues with something new [Part1]

[Quentin Colombet via llvm-commits]

Hi Mikhail,

Could you check how this patch impacts our performance?

Thanks,
-Quentin

> On Jan 29, 2016, at 9:48 AM, Wei Mi <wmi at google.com> wrote:
> 
> wmi updated this revision to Diff 46392.
> wmi marked an inline comment as done.
> wmi added a comment.
> 
> Add SM_Speed split mode and use it as default. SM_Size sometimes will hoist spills from cold region in inner loop to hot region in outer loop, which is bad for performance.   SM_Speed will only try to hoist spills from hot region to cold region. If it fails to hoist all the spills to a cold place, step back and remove spills dominated by others.
> 
> Compare "hoistSpill + split-spill-mode=speed" with "hoistSpill + split-spill-mode=size", an internal benchmark gets 1.5% improvement. llvm testsuite has no perf change.
> 
> 
> Repository:
>  rL LLVM
> 
> http://reviews.llvm.org/D15302
> 
> Files:
>  include/llvm/CodeGen/LiveRangeEdit.h
>  lib/CodeGen/InlineSpiller.cpp
>  lib/CodeGen/LiveRangeEdit.cpp
>  lib/CodeGen/RegAllocGreedy.cpp
>  lib/CodeGen/Spiller.h
>  lib/CodeGen/SplitKit.cpp
>  lib/CodeGen/SplitKit.h
>  test/CodeGen/AArch64/aarch64-deferred-spilling.ll
>  test/CodeGen/ARM/subreg-remat.ll
>  test/CodeGen/SPARC/spill.ll
>  test/CodeGen/X86/avx512-bugfix-25270.ll
>  test/CodeGen/X86/fold-push.ll
>  test/CodeGen/X86/hoist-spill.ll
>  test/CodeGen/X86/new-remat.ll
>  test/CodeGen/X86/ragreedy-hoist-spill.ll
>  test/CodeGen/X86/vselect-minmax.ll
> 
> <D15302.46392.patch>