[PATCH] D16603: AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions

[Tom Stellard via llvm-commits]

tstellarAMD marked 8 inline comments as done.

================
Comment at: lib/Target/AMDGPU/SIFixSGPRLiveRanges.cpp:115
@@ +114,3 @@
+                                          E = MBB->end(); I != E; ++I) {
+      if (!TII->isSOPP(I->getOpcode()))
+        return false;
----------------
arsenm wrote:
> You should use TII->isSOPP(*I) here.
> 
> I think there should be an assert that I->isBranch()
You mean the assert should be inside the branch?

================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:2924-2925
@@ +2923,4 @@
+
+    if (I->getOpcode() == AMDGPU::S_CBRANCH_SCC0 ||
+        I->getOpcode() == AMDGPU::S_CBRANCH_SCC1)
+      Worklist.push_back(I);
----------------
arsenm wrote:
> Why is this limited to branches? What if you had another user like a s_cselect? I would expect any user to need processing
If we don't limit this to branch instructions, then any instructions in the block which read scc will be moved to VALU, which we don't want.  For most instructions the decision to move them to the VALU is based on explicit uses.  This function needs to handle the cases where changing and implicit uses would force the instruction to go to the VALU.

================
Comment at: test/CodeGen/AMDGPU/si-annotate-cf.ll:43-46
@@ -41,5 +42,6 @@
 
-define void @phi_cond_outside_loop(i32 %a, i32 %b) {
+define void @phi_cond_outside_loop(i32 %b) {
 entry:
-  %0 = icmp eq i32 %a , 0
+  %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
+  %0 = icmp eq i32 %tid , 0
   br i1 %0, label %if, label %else
----------------
arsenm wrote:
> Why this test change and the others like it?
Most of the tests with branching assume divergent branches, but with these changes most branches are uniform, so I forced branches to be divergent in places where the test assumes divergence.


http://reviews.llvm.org/D16603