[llvm] r259202 - [mips] Absolute value macro expansion

[Zoran Jovanovic via llvm-commits]

Author: zjovanovic
Date: Fri Jan 29 10:18:34 2016
New Revision: 259202

URL: http://llvm.org/viewvc/llvm-project?rev=259202&view=rev
Log:
[mips] Absolute value macro expansion

Author: obucina
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D16323

Added:
    llvm/trunk/test/MC/Mips/macro-abs.s
Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=259202&r1=259201&r2=259202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Fri Jan 29 10:18:34 2016
@@ -233,6 +233,9 @@ class MipsAsmParser : public MCTargetAsm
   bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
                           SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandAbs(MCInst &Inst, SMLoc IDLoc,
+                 SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
@@ -2087,6 +2090,9 @@ MipsAsmParser::tryExpandInstruction(MCIn
   case Mips::DRORImm:
     return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail
                                                          : MER_Success;
+  case Mips::ABSMacro:
+    return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail
+                                                : MER_Success;
   }
 }
 
@@ -3531,6 +3537,22 @@ bool MipsAsmParser::expandDRotationImm(M
   return true;
 }
 
+bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc,
+                              SmallVectorImpl<MCInst> &Instructions) {
+
+  unsigned FirstRegOp = Inst.getOperand(0).getReg();
+  unsigned SecondRegOp = Inst.getOperand(1).getReg();
+
+  emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, Instructions);
+  if (FirstRegOp != SecondRegOp)
+    emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions);
+  else
+    createNop(false, IDLoc, Instructions);
+  emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions);
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   if (hasShortDelaySlot)

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=259202&r1=259201&r2=259202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Jan 29 10:18:34 2016
@@ -1808,6 +1808,9 @@ def : MipsInstAlias<"dror $rd, $rs",
 def : MipsInstAlias<"dror $rd, $imm",
                     (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
 
+def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
+                                 "abs\t$rd, $rs">;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//

Added: llvm/trunk/test/MC/Mips/macro-abs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-abs.s?rev=259202&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-abs.s (added)
+++ llvm/trunk/test/MC/Mips/macro-abs.s Fri Jan 29 10:18:34 2016
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple mips-unknown-linux -show-encoding %s | FileCheck %s
+
+.text
+# CHECK:    .text
+  abs $4, $4
+# CHECK:    bgez    $4, 8       # encoding: [0x04,0x81,0x00,0x02]
+# CHECK:    nop                 # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:    neg     $4, $4      # encoding: [0x00,0x04,0x20,0x22]
+  abs $4, $5
+# CHECK:    bgez    $5, 8       # encoding: [0x04,0xa1,0x00,0x02]
+# CHECK:    move    $4, $5      # encoding: [0x00,0xa0,0x20,0x21]
+# CHECK:    neg     $4, $5      # encoding: [0x00,0x05,0x20,0x22]