[PATCH] D16110: [Power9] Implement new vsx instructions: quad-precision move, fp-arithmetic

Chuang-Yu Cheng via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 29 06:58:06 PST 2016


cycheng added inline comments.

================
Comment at: lib/Target/PowerPC/PPCInstrFormats.td:750
@@ -749,1 +749,3 @@
 
+// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RC]
+class XForm_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo,
----------------
nemanjai wrote:
> PO == Opcode?
Yes! It is used in Power ISA, section 1.6.x


http://reviews.llvm.org/D16110





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