[PATCH] D16592: Fix for PR26180

[Nemanja Ivanovic via llvm-commits]

nemanjai updated this revision to Diff 46378.
nemanjai added a comment.

Added a test case


Repository:
  rL LLVM

http://reviews.llvm.org/D16592

Files:
  lib/Target/PowerPC/PPCFastISel.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCSubtarget.cpp
  test/CodeGen/PowerPC/pr26180.ll

Index: test/CodeGen/PowerPC/pr26180.ll
===================================================================
--- test/CodeGen/PowerPC/pr26180.ll
+++ test/CodeGen/PowerPC/pr26180.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s --check-prefix=GENERIC
+; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s
+
+define i32 @bad(double %x) {
+  %1 = fptoui double %x to i32
+  ret i32 %1
+}
+
+; CHECK: fctidz 1, 1
+; CHECK: stfd 1, [[OFF:.*]](1)
+; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
+; GENERIC: fctiwuz 1, 1
+; GENERIC: stfd 1, [[OFF:.*]](1)
+; GENERIC: lwz {{[0-9]*}}, [[OFF]](1)
Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp
+++ lib/Target/PowerPC/PPCSubtarget.cpp
@@ -108,7 +108,7 @@
 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
-  if (CPUName.empty()) {
+  if (CPUName.empty() || CPU == "generic") {
     // If cross-compiling with -march=ppc64le without -mcpu
     if (TargetTriple.getArch() == Triple::ppc64le)
       CPUName = "ppc64le";
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6160,11 +6160,11 @@
                          MPI, false, false, 0);
 
   // Result is a load from the stack slot.  If loading 4 bytes, make sure to
-  // add in a bias.
+  // add in a bias on big endian.
   if (Op.getValueType() == MVT::i32 && !i32Stack) {
     FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
                         DAG.getConstant(4, dl, FIPtr.getValueType()));
-    MPI = MPI.getWithOffset(4);
+    MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4);
   }
 
   RLI.Chain = Chain;
Index: lib/Target/PowerPC/PPCFastISel.cpp
===================================================================
--- lib/Target/PowerPC/PPCFastISel.cpp
+++ lib/Target/PowerPC/PPCFastISel.cpp
@@ -1068,10 +1068,10 @@
   if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
     return 0;
 
-  // Reload it into a GPR.  If we want an i32, modify the address
-  // to have a 4-byte offset so we load from the right place.
+  // Reload it into a GPR.  If we want an i32 on big endian, modify the
+  // address to have a 4-byte offset so we load from the right place.
   if (VT == MVT::i32)
-    Addr.Offset = 4;
+    Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
 
   // Look at the currently assigned register for this instruction
   // to determine the required register class.


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