[llvm] r259176 - Fix up conditional formatting.

[Eric Christopher via llvm-commits]

Author: echristo
Date: Fri Jan 29 01:19:49 2016
New Revision: 259176

URL: http://llvm.org/viewvc/llvm-project?rev=259176&view=rev
Log:
Fix up conditional formatting.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=259176&r1=259175&r2=259176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Fri Jan 29 01:19:49 2016
@@ -2071,7 +2071,6 @@ unsigned PPCFastISel::PPCMaterialize64Bi
   return TmpReg3;
 }
 
-
 // Materialize an integer constant into a register, and return
 // the register number (or zero if we failed to handle it).
 unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
@@ -2085,12 +2084,12 @@ unsigned PPCFastISel::PPCMaterializeInt(
     return ImmReg;
   }
 
-  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
-      VT != MVT::i8 && VT != MVT::i1) 
+  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
+      VT != MVT::i1)
     return 0;
 
-  const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
-                                   &PPC::GPRCRegClass);
+  const TargetRegisterClass *RC =
+      ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
 
   // If the constant is in range, use a load-immediate.
   if (UseSExt && isInt<16>(CI->getSExtValue())) {