[PATCH] D16323: [mips] Absolute value macro expansion

[Srdjan Obucina via llvm-commits]

obucina updated this revision to Diff 46001.
obucina added a comment.

New diff contains suggested changes


http://reviews.llvm.org/D16323

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  lib/Target/Mips/MipsInstrInfo.td
  test/MC/Mips/macro-abs.s

Index: test/MC/Mips/macro-abs.s
===================================================================
--- test/MC/Mips/macro-abs.s
+++ test/MC/Mips/macro-abs.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple mips-unknown-linux -show-encoding %s | FileCheck %s
+
+.text
+# CHECK:    .text
+  abs $4, $4
+# CHECK:    bgez    $4, 8       # encoding: [0x04,0x81,0x00,0x02]
+# CHECK:    nop                 # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:    neg     $4, $4      # encoding: [0x00,0x04,0x20,0x22]
+  abs $4, $5
+# CHECK:    bgez    $5, 8       # encoding: [0x04,0xa1,0x00,0x02]
+# CHECK:    move    $4, $5      # encoding: [0x00,0xa0,0x20,0x21]
+# CHECK:    neg     $4, $5      # encoding: [0x00,0x05,0x20,0x22]
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1808,6 +1808,9 @@
 def : MipsInstAlias<"dror $rd, $imm",
                     (DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
 
+def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
+                                 "abs\t$rd, $rs">;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -233,6 +233,9 @@
   bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
                           SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandAbs(MCInst &Inst, SMLoc IDLoc,
+                 SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
@@ -2087,6 +2090,9 @@
   case Mips::DRORImm:
     return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail
                                                          : MER_Success;
+  case Mips::ABSMacro:
+    return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail
+                                                : MER_Success;
   }
 }
 
@@ -3521,6 +3527,22 @@
   return true;
 }
 
+bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc,
+                              SmallVectorImpl<MCInst> &Instructions) {
+
+  unsigned FirstRegOp = Inst.getOperand(0).getReg();
+  unsigned SecondRegOp = Inst.getOperand(1).getReg();
+
+  emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, Instructions);
+  if (FirstRegOp != SecondRegOp)
+    emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions);
+  else
+    createNop(false, IDLoc, Instructions);
+  emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions);
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   if (hasShortDelaySlot)


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