[llvm] r258614 - AMDGPU: Replace some deprecated intrinsic uses in tests
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 22 21:42:49 PST 2016
Author: arsenm
Date: Fri Jan 22 23:42:49 2016
New Revision: 258614
URL: http://llvm.org/viewvc/llvm-project?rev=258614&view=rev
Log:
AMDGPU: Replace some deprecated intrinsic uses in tests
Modified:
llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll
llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll
llvm/trunk/test/CodeGen/AMDGPU/load-input-fold.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll
llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll
llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll
llvm/trunk/test/Transforms/StructurizeCFG/nested-loop-order.ll
Modified: llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/big_alu.ll Fri Jan 22 23:42:49 2016
@@ -216,20 +216,20 @@ ENDIF136:
%198 = fadd float %197, %196
%199 = fmul float 0xBE5EFB4CC0000000, %182
%200 = fmul float %199, %182
- %201 = call float @llvm.AMDIL.exp.(float %200)
+ %201 = call float @llvm.exp2.f32(float %200)
%one.sub.a.i = fsub float 1.000000e+00, %201
%one.sub.ac.i = fmul float %one.sub.a.i, 0x3FA99999A0000000
%mul.i = fmul float %198, 0x3FA99999A0000000
%result.i = fadd float %mul.i, %one.sub.ac.i
%202 = fadd float %result.i, 0x3FF4CCCCC0000000
%203 = fmul float %202, 0x3FE1C71C80000000
- %204 = call float @llvm.AMDIL.clamp.(float %203, float 0.000000e+00, float 1.000000e+00)
+ %204 = call float @llvm.AMDGPU.clamp.f32(float %203, float 0.000000e+00, float 1.000000e+00)
%205 = fadd float %result.i, 0x3FF4CCCCC0000000
%206 = fmul float %205, 0x3FE1C71C80000000
- %207 = call float @llvm.AMDIL.clamp.(float %206, float 0.000000e+00, float 1.000000e+00)
+ %207 = call float @llvm.AMDGPU.clamp.f32(float %206, float 0.000000e+00, float 1.000000e+00)
%208 = fadd float %result.i, 2.000000e+00
%209 = fmul float %208, 0x3FD611A7A0000000
- %210 = call float @llvm.AMDIL.clamp.(float %209, float 0.000000e+00, float 1.000000e+00)
+ %210 = call float @llvm.AMDGPU.clamp.f32(float %209, float 0.000000e+00, float 1.000000e+00)
%211 = fmul float 2.000000e+00, %204
%212 = fsub float -0.000000e+00, %211
%213 = fadd float 3.000000e+00, %212
@@ -279,13 +279,13 @@ ENDIF136:
%257 = fmul float %253, 0.000000e+00
%258 = fadd float %result.i, 0x3FF4CCCCC0000000
%259 = fmul float %258, 0x3FE1C71C80000000
- %260 = call float @llvm.AMDIL.clamp.(float %259, float 0.000000e+00, float 1.000000e+00)
+ %260 = call float @llvm.AMDGPU.clamp.f32(float %259, float 0.000000e+00, float 1.000000e+00)
%261 = fadd float %result.i, 0x3FF4CCCCC0000000
%262 = fmul float %261, 0x3FE1C71C80000000
- %263 = call float @llvm.AMDIL.clamp.(float %262, float 0.000000e+00, float 1.000000e+00)
+ %263 = call float @llvm.AMDGPU.clamp.f32(float %262, float 0.000000e+00, float 1.000000e+00)
%264 = fadd float %result.i, 2.000000e+00
%265 = fmul float %264, 0x3FD611A7A0000000
- %266 = call float @llvm.AMDIL.clamp.(float %265, float 0.000000e+00, float 1.000000e+00)
+ %266 = call float @llvm.AMDGPU.clamp.f32(float %265, float 0.000000e+00, float 1.000000e+00)
%267 = fmul float 2.000000e+00, %260
%268 = fsub float -0.000000e+00, %267
%269 = fadd float 3.000000e+00, %268
@@ -386,7 +386,7 @@ ENDIF136:
%364 = fadd float %363, %362
%365 = fadd float %364, 0xBFEFAE1480000000
%366 = fmul float %365, 0xC023FFFFC0000000
- %367 = call float @llvm.AMDIL.clamp.(float %366, float 0.000000e+00, float 1.000000e+00)
+ %367 = call float @llvm.AMDGPU.clamp.f32(float %366, float 0.000000e+00, float 1.000000e+00)
%368 = fsub float -0.000000e+00, %334
%369 = fadd float %result.i, %368
%370 = fadd float %369, 0x3FBEB851E0000000
@@ -412,7 +412,7 @@ ENDIF136:
%390 = fadd float %389, %388
%391 = fadd float %390, 0xBFEFAE1480000000
%392 = fmul float %391, 0xC0490001A0000000
- %393 = call float @llvm.AMDIL.clamp.(float %392, float 0.000000e+00, float 1.000000e+00)
+ %393 = call float @llvm.AMDGPU.clamp.f32(float %392, float 0.000000e+00, float 1.000000e+00)
%394 = fmul float 2.000000e+00, %367
%395 = fsub float -0.000000e+00, %394
%396 = fadd float 3.000000e+00, %395
@@ -1146,7 +1146,7 @@ IF179:
%870 = fadd float %869, %868
%871 = fadd float %870, 0xBFEFAE1480000000
%872 = fmul float %871, 0xC043FFFE20000000
- %873 = call float @llvm.AMDIL.clamp.(float %872, float 0.000000e+00, float 1.000000e+00)
+ %873 = call float @llvm.AMDGPU.clamp.f32(float %872, float 0.000000e+00, float 1.000000e+00)
%874 = fmul float 2.000000e+00, %873
%875 = fsub float -0.000000e+00, %874
%876 = fadd float 3.000000e+00, %875
@@ -1250,7 +1250,7 @@ ENDIF178:
%932 = fmul float %931, %929
%933 = fmul float %932, %929
%934 = fmul float %933, 0x3FF7154760000000
- %935 = call float @llvm.AMDIL.exp.(float %934)
+ %935 = call float @llvm.exp2.f32(float %934)
%936 = fcmp oeq float %53, 1.000000e+00
%937 = sext i1 %936 to i32
%938 = bitcast i32 %937 to float
@@ -1289,11 +1289,10 @@ declare <4 x float> @llvm.AMDGPU.tex(<4
; Function Attrs: readonly
declare float @fabs(float) #4
-; Function Attrs: readnone
-declare float @llvm.AMDIL.exp.(float) #2
+declare float @llvm.exp2.f32(float) #3
; Function Attrs: readnone
-declare float @llvm.AMDIL.clamp.(float, float, float) #2
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) #2
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Modified: llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/kcache-fold.ll Fri Jan 22 23:42:49 2016
@@ -36,10 +36,10 @@ main_body:
%29 = extractelement <4 x float> %28, i32 3
%30 = fcmp ogt float %25, 0.000000e+00
%31 = select i1 %30, float %27, float %29
- %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
- %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
- %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
+ %32 = call float @llvm.AMDGPU.clamp.f32(float %7, float 0.000000e+00, float 1.000000e+00)
+ %33 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00)
+ %34 = call float @llvm.AMDGPU.clamp.f32(float %23, float 0.000000e+00, float 1.000000e+00)
+ %35 = call float @llvm.AMDGPU.clamp.f32(float %31, float 0.000000e+00, float 1.000000e+00)
%36 = insertelement <4 x float> undef, float %32, i32 0
%37 = insertelement <4 x float> %36, float %33, i32 1
%38 = insertelement <4 x float> %37, float %34, i32 2
@@ -84,10 +84,10 @@ main_body:
%29 = extractelement <4 x float> %28, i32 2
%30 = fcmp ogt float %25, 0.000000e+00
%31 = select i1 %30, float %27, float %29
- %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
- %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
- %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
+ %32 = call float @llvm.AMDGPU.clamp.f32(float %7, float 0.000000e+00, float 1.000000e+00)
+ %33 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00)
+ %34 = call float @llvm.AMDGPU.clamp.f32(float %23, float 0.000000e+00, float 1.000000e+00)
+ %35 = call float @llvm.AMDGPU.clamp.f32(float %31, float 0.000000e+00, float 1.000000e+00)
%36 = insertelement <4 x float> undef, float %32, i32 0
%37 = insertelement <4 x float> %36, float %33, i32 1
%38 = insertelement <4 x float> %37, float %34, i32 2
@@ -96,5 +96,5 @@ main_body:
ret void
}
-declare float @llvm.AMDIL.clamp.(float, float, float) readnone
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-input-fold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-input-fold.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-input-fold.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-input-fold.ll Fri Jan 22 23:42:49 2016
@@ -104,7 +104,7 @@ declare float @fabs(float) #2
declare float @llvm.AMDGPU.rsq(float) #1
; Function Attrs: readnone
-declare float @llvm.AMDIL.clamp.(float, float, float) #1
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1
; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3
Modified: llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll Fri Jan 22 23:42:49 2016
@@ -44,10 +44,10 @@ ENDIF:
%temp1.0 = phi float [ %., %IF ], [ %48, %ELSE17 ], [ 0.000000e+00, %ELSE ]
%temp2.0 = phi float [ 0.000000e+00, %IF ], [ %49, %ELSE17 ], [ 1.000000e+00, %ELSE ]
%temp.0 = phi float [ %.18, %IF ], [ %47, %ELSE17 ], [ 0.000000e+00, %ELSE ]
- %27 = call float @llvm.AMDIL.clamp.(float %temp.0, float 0.000000e+00, float 1.000000e+00)
- %28 = call float @llvm.AMDIL.clamp.(float %temp1.0, float 0.000000e+00, float 1.000000e+00)
- %29 = call float @llvm.AMDIL.clamp.(float %temp2.0, float 0.000000e+00, float 1.000000e+00)
- %30 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
+ %27 = call float @llvm.AMDGPU.clamp.f32(float %temp.0, float 0.000000e+00, float 1.000000e+00)
+ %28 = call float @llvm.AMDGPU.clamp.f32(float %temp1.0, float 0.000000e+00, float 1.000000e+00)
+ %29 = call float @llvm.AMDGPU.clamp.f32(float %temp2.0, float 0.000000e+00, float 1.000000e+00)
+ %30 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
%31 = insertelement <4 x float> undef, float %27, i32 0
%32 = insertelement <4 x float> %31, float %28, i32 1
%33 = insertelement <4 x float> %32, float %29, i32 2
@@ -74,7 +74,7 @@ ELSE17:
br label %ENDIF
}
-declare float @llvm.AMDIL.clamp.(float, float, float) #0
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Modified: llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll Fri Jan 22 23:42:49 2016
@@ -43,10 +43,10 @@ LOOP:
br i1 %29, label %IF, label %LOOP29
IF: ; preds = %LOOP
- %30 = call float @llvm.AMDIL.clamp.(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
- %31 = call float @llvm.AMDIL.clamp.(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
- %32 = call float @llvm.AMDIL.clamp.(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
- %33 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
+ %30 = call float @llvm.AMDGPU.clamp.f32(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
+ %31 = call float @llvm.AMDGPU.clamp.f32(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
+ %32 = call float @llvm.AMDGPU.clamp.f32(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
+ %33 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
%34 = insertelement <4 x float> undef, float %30, i32 0
%35 = insertelement <4 x float> %34, float %31, i32 1
%36 = insertelement <4 x float> %35, float %32, i32 2
@@ -81,7 +81,7 @@ ENDIF30:
br label %LOOP29
}
-declare float @llvm.AMDIL.clamp.(float, float, float) #0
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Modified: llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-fs-loop.ll Fri Jan 22 23:42:49 2016
@@ -30,10 +30,10 @@ LOOP:
br i1 %16, label %IF, label %ENDIF
IF: ; preds = %LOOP
- %17 = call float @llvm.AMDIL.clamp.(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
- %18 = call float @llvm.AMDIL.clamp.(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
- %19 = call float @llvm.AMDIL.clamp.(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
- %20 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
+ %17 = call float @llvm.AMDGPU.clamp.f32(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
+ %18 = call float @llvm.AMDGPU.clamp.f32(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
+ %19 = call float @llvm.AMDGPU.clamp.f32(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
+ %20 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
%21 = insertelement <4 x float> undef, float %17, i32 0
%22 = insertelement <4 x float> %21, float %18, i32 1
%23 = insertelement <4 x float> %22, float %19, i32 2
@@ -48,7 +48,7 @@ ENDIF:
br label %LOOP
}
-declare float @llvm.AMDIL.clamp.(float, float, float) #0
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Modified: llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll Fri Jan 22 23:42:49 2016
@@ -95,7 +95,7 @@ main_body:
IF: ; preds = %main_body
%tmp77 = fsub float -0.000000e+00, %tmp69
- %tmp78 = call float @llvm.AMDIL.exp.(float %tmp77)
+ %tmp78 = call float @llvm.exp2.f32(float %tmp77)
%tmp79 = fsub float -0.000000e+00, %tmp78
%tmp80 = fadd float 1.000000e+00, %tmp79
%tmp81 = fdiv float 1.000000e+00, %tmp69
@@ -115,7 +115,7 @@ ENDIF:
IF25: ; preds = %ENDIF
%tmp90 = fsub float -0.000000e+00, %tmp70
- %tmp91 = call float @llvm.AMDIL.exp.(float %tmp90)
+ %tmp91 = call float @llvm.exp2.f32(float %tmp90)
%tmp92 = fsub float -0.000000e+00, %tmp91
%tmp93 = fadd float 1.000000e+00, %tmp92
%tmp94 = fdiv float 1.000000e+00, %tmp70
@@ -205,8 +205,7 @@ declare <4 x float> @llvm.SI.sample.v2i3
; Function Attrs: readnone
declare float @llvm.amdgcn.rsq.f32(float) #3
-; Function Attrs: readnone
-declare float @llvm.AMDIL.exp.(float) #3
+declare float @llvm.exp2.f32(float) #1
; Function Attrs: nounwind readnone
declare float @llvm.pow.f32(float, float) #1
Modified: llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll Fri Jan 22 23:42:49 2016
@@ -839,10 +839,10 @@ main_body:
%tmp194 = call float @llvm.SI.fs.interp(i32 3, i32 7, i32 %arg4, <2 x i32> %arg6)
%tmp195 = fmul float %arg14, %tmp123
%tmp196 = fadd float %tmp195, %tmp124
- %tmp197 = call float @llvm.AMDIL.clamp.(float %tmp162, float 0.000000e+00, float 1.000000e+00)
- %tmp198 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %tmp199 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
- %tmp200 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
+ %tmp197 = call float @llvm.AMDGPU.clamp.f32(float %tmp162, float 0.000000e+00, float 1.000000e+00)
+ %tmp198 = call float @llvm.AMDGPU.clamp.f32(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
+ %tmp199 = call float @llvm.AMDGPU.clamp.f32(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
+ %tmp200 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
%tmp201 = bitcast float %tmp197 to i32
%tmp202 = icmp ne i32 %tmp201, 0
%. = select i1 %tmp202, float -1.000000e+00, float 1.000000e+00
@@ -897,9 +897,9 @@ main_body:
%tmp245 = fadd float %tmp244, %tmp243
%tmp246 = fmul float %tmp217, %tmp191
%tmp247 = fadd float %tmp245, %tmp246
- %tmp248 = call float @llvm.AMDIL.clamp.(float %tmp247, float 0.000000e+00, float 1.000000e+00)
+ %tmp248 = call float @llvm.AMDGPU.clamp.f32(float %tmp247, float 0.000000e+00, float 1.000000e+00)
%tmp249 = fmul float %tmp213, 0x3F5A36E2E0000000
- %tmp250 = call float @llvm.AMDIL.clamp.(float %tmp249, float 0.000000e+00, float 1.000000e+00)
+ %tmp250 = call float @llvm.AMDGPU.clamp.f32(float %tmp249, float 0.000000e+00, float 1.000000e+00)
%tmp251 = fsub float -0.000000e+00, %tmp250
%tmp252 = fadd float 1.000000e+00, %tmp251
%tmp253 = call float @llvm.pow.f32(float %tmp248, float 2.500000e-01)
@@ -1104,7 +1104,7 @@ IF189:
%tmp426 = fadd float %tmp424, %tmp425
%tmp427 = fsub float -0.000000e+00, %tmp426
%tmp428 = fadd float 0x3FF00068E0000000, %tmp427
- %tmp429 = call float @llvm.AMDIL.clamp.(float %tmp428, float 0.000000e+00, float 1.000000e+00)
+ %tmp429 = call float @llvm.AMDGPU.clamp.f32(float %tmp428, float 0.000000e+00, float 1.000000e+00)
%tmp430 = call float @llvm.amdgcn.rsq.f32(float %tmp429)
%tmp431 = fmul float %tmp430, %tmp429
%tmp432 = fsub float -0.000000e+00, %tmp429
@@ -1179,7 +1179,7 @@ ENDIF197:
%tmp491 = extractelement <4 x float> %tmp487, i32 3
%tmp492 = fmul float %tmp491, 3.200000e+01
%tmp493 = fadd float %tmp492, -1.600000e+01
- %tmp494 = call float @llvm.AMDIL.exp.(float %tmp493)
+ %tmp494 = call float @llvm.exp2.f32(float %tmp493)
%tmp495 = fmul float %tmp488, %tmp494
%tmp496 = fmul float %tmp489, %tmp494
%tmp497 = fmul float %tmp490, %tmp494
@@ -1222,7 +1222,7 @@ ENDIF197:
%tmp534 = fadd float %tmp533, %tmp532
%tmp535 = fmul float %temp14.0, %tmp531
%tmp536 = fadd float %tmp534, %tmp535
- %tmp537 = call float @llvm.AMDIL.clamp.(float %tmp536, float 0.000000e+00, float 1.000000e+00)
+ %tmp537 = call float @llvm.AMDGPU.clamp.f32(float %tmp536, float 0.000000e+00, float 1.000000e+00)
%tmp538 = fmul float %tmp364, %tmp537
%tmp539 = fmul float %tmp365, %tmp537
%tmp540 = fmul float %tmp366, %tmp537
@@ -1369,7 +1369,7 @@ ENDIF209:
%tmp649 = fadd float %temp80.0, -1.000000e+00
%tmp650 = fmul float %tmp649, %tmp76
%tmp651 = fadd float %tmp650, 1.000000e+00
- %tmp652 = call float @llvm.AMDIL.clamp.(float %tmp651, float 0.000000e+00, float 1.000000e+00)
+ %tmp652 = call float @llvm.AMDGPU.clamp.f32(float %tmp651, float 0.000000e+00, float 1.000000e+00)
%tmp653 = bitcast float %tmp642 to i32
%tmp654 = bitcast float %tmp644 to i32
%tmp655 = bitcast float 0.000000e+00 to i32
@@ -1404,8 +1404,8 @@ ENDIF209:
%tmp684 = fadd float %tmp683, %temp89.0
%tmp685 = fmul float %tmp640, %temp90.0
%tmp686 = fadd float %tmp685, %temp91.0
- %tmp687 = call float @llvm.AMDIL.clamp.(float %tmp684, float 0.000000e+00, float 1.000000e+00)
- %tmp688 = call float @llvm.AMDIL.clamp.(float %tmp686, float 0.000000e+00, float 1.000000e+00)
+ %tmp687 = call float @llvm.AMDGPU.clamp.f32(float %tmp684, float 0.000000e+00, float 1.000000e+00)
+ %tmp688 = call float @llvm.AMDGPU.clamp.f32(float %tmp686, float 0.000000e+00, float 1.000000e+00)
%tmp689 = fsub float -0.000000e+00, %tmp687
%tmp690 = fadd float %tmp661, %tmp689
%tmp691 = fsub float -0.000000e+00, %tmp688
@@ -1447,7 +1447,7 @@ ENDIF209:
%tmp721 = call float @llvm.pow.f32(float %result.i28, float %tmp75)
%tmp722 = fmul float %tmp721, %tmp78
%tmp723 = fadd float %tmp722, %tmp79
- %tmp724 = call float @llvm.AMDIL.clamp.(float %tmp723, float 0.000000e+00, float 1.000000e+00)
+ %tmp724 = call float @llvm.AMDGPU.clamp.f32(float %tmp723, float 0.000000e+00, float 1.000000e+00)
%tmp725 = fmul float %tmp724, %tmp724
%tmp726 = fmul float 2.000000e+00, %tmp724
%tmp727 = fsub float -0.000000e+00, %tmp726
@@ -1487,7 +1487,7 @@ ENDIF209:
%tmp751 = fmul float %tmp750, %tmp750
%tmp752 = fmul float %tmp751, %tmp49
%tmp753 = fadd float %tmp752, %tmp50
- %tmp754 = call float @llvm.AMDIL.clamp.(float %tmp753, float 0.000000e+00, float 1.000000e+00)
+ %tmp754 = call float @llvm.AMDGPU.clamp.f32(float %tmp753, float 0.000000e+00, float 1.000000e+00)
%tmp755 = fsub float -0.000000e+00, %tmp754
%tmp756 = fadd float 1.000000e+00, %tmp755
%tmp757 = fmul float %tmp32, %tmp756
@@ -1524,7 +1524,7 @@ ENDIF209:
%tmp772 = select i1 %tmp771, float 6.550400e+04, float %tmp766
%tmp773 = fmul float %result.i2, %tmp51
%tmp774 = fadd float %tmp773, %tmp52
- %tmp775 = call float @llvm.AMDIL.clamp.(float %tmp774, float 0.000000e+00, float 1.000000e+00)
+ %tmp775 = call float @llvm.AMDGPU.clamp.f32(float %tmp774, float 0.000000e+00, float 1.000000e+00)
%tmp776 = call i32 @llvm.SI.packf16(float %tmp768, float %tmp770)
%tmp777 = bitcast i32 %tmp776 to float
%tmp778 = call i32 @llvm.SI.packf16(float %tmp772, float %tmp775)
@@ -1546,7 +1546,7 @@ ELSE214:
}
; Function Attrs: readnone
-declare float @llvm.AMDIL.clamp.(float, float, float) #1
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1
; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #2
@@ -1554,8 +1554,7 @@ declare <4 x float> @llvm.SI.sample.v2i3
; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #2
-; Function Attrs: readnone
-declare float @llvm.AMDIL.exp.(float) #1
+declare float @llvm.exp2.f32(float) #2
; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #2
Modified: llvm/trunk/test/Transforms/StructurizeCFG/nested-loop-order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StructurizeCFG/nested-loop-order.ll?rev=258614&r1=258613&r2=258614&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/StructurizeCFG/nested-loop-order.ll (original)
+++ llvm/trunk/test/Transforms/StructurizeCFG/nested-loop-order.ll Fri Jan 22 23:42:49 2016
@@ -67,7 +67,7 @@ ENDIF28:
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
; Function Attrs: readnone
-declare float @llvm.AMDIL.clamp.(float, float, float) #2
+declare float @llvm.AMDGPU.clamp.f32(float, float, float) #2
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
More information about the llvm-commits
mailing list