[PATCH] D16291: AArch64: Implement missed conditional compare sequences.

[Matthias Braun via llvm-commits]

MatzeB added a comment.

This looks like the right direction now, however I believe that you can shorten tryLowerToAArch64Cmp() as noted below. I'd also recommend rebaseing llvm to get r258605 (I found I bug in my ccmp creation code while re-reading it during review).


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:1557-1571
@@ +1556,17 @@
+static SDValue tryLowerToAArch64Cmp(SDValue Op, SelectionDAG &DAG) {
+  EVT VT = Op.getValueType();
+  if (!Op->hasOneUse())
+    return Op;
+
+  SDLoc DL(Op);
+  SDValue LHS = Op.getOperand(0);
+  SDValue RHS = Op.getOperand(1);
+  if ((LHS.getOpcode() != ISD::SETCC) || (RHS.getOpcode() != ISD::SETCC))
+    return Op;
+
+  bool canPushNegate;
+  if (!isConjunctionDisjunctionTree(LHS, canPushNegate))
+    return SDValue();
+  if (!isConjunctionDisjunctionTree(RHS, canPushNegate))
+    return SDValue();
+
----------------
I would assume that you can replace the first part of this function with:
```
bool Dummy;
if (!isConjunctionDisjunctionTree(Op, Dummy))
   return SDValue();
```
That would be shorter and give let the function bail out on some subtrees that cannot be represented with ccmp sequences (not a correctness problem but you would generate unnecessary csels below if you cannot use ccmp anyway).


http://reviews.llvm.org/D16291